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copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 august, 2005 net2272 local bus to usb 2.0 peripheral controller patent pending for revision 1a data book version 1.91 august 2005 website www.plxtech.com technical support www.plxtech.com/support/ phone 408 774-9060 800 759-3735 fax 408 774-2169
copyright information copyright? 2003, 2004, and 2005 plx technology, inc. all rights reserved. the information in this document is proprietary and confidential to plx technology. no part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from plx technology. plx technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. while the information contained herein is believed to be accurate, such in formation is preliminar y, and no representations or warranties of accuracy or completeness are made. in no event wi ll plx technology be liable for damages arising directly or indirectly from any us e of or reliance upon the informati on contained in this document. plx technology may make improvements or changes in th e product(s) and/or the program(s) described in this documentation at any time. plx technology retains the right to make changes to this product at any time, without notice. products may have minor variations to this publication, known as errata. plx technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of plx technology products. plx technology, the plx logo, and data pipe ar chitecture are registered trademarks of plx technology, inc. pci express is a tradem ark of the pci special interest group. all product names are trademarks, re gistered trademarks, or servicem arks of their respective owners. copyright information plx technology, inc. ii net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91
august, 2005 revision history net2272 local bus to usb 2.0 peripheral controller data book iii copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 revision history version date description of changes 1.0 may 5, 2003 silicon initial release. 1.1 october 7, 2003 silicon release. 1.2 october 15, 2003 powe r consumption update. 1.3 june 15, 2004 minor clarifications. 1.4 february 17, 2005 increased dm a burst write recovery time. added fbga package. 1.5 march 18, 2005 added 2.5v i/ o electrical specifications. 1.6 april 13, 2005 changed temperatur e references from industrial to commercial (includes change to bga ordering number). moved nand tree test to new chapter 10. reorganized chapter 11, elec trical specifications, and created separate set of 2.5v and 3.3v vddio test condition tables. applied miscellaneous corrections and changes for readability and consistency. 1.7 may 27, 2005 added 1.8v i/o electrical specifications. reorganized chapter 11, electrical specifications to reflect the usb r2.0 specification table sequences. moved physical pin assignmen t figures from chapter 2 to chapter 12. applied miscellaneous corrections and changes for readability and consistency. 1.8 june 10, 2005 corrected 1.8v-related content. replaced chapter 11 dc specification. 1.9 august 10, 2005 revised crysta l note in section 1.4.1. updated vddio local bus ac sp ecifications for all three voltages. added ordering p/n expl anation to appendix a. 1.91 august 18, 2005 moved the physical pin and ball assignment diagrams from chapter 12 to chapter 2. appended ?at 3.3v vddio? to ti tle of sections 4.5.5 and 4.6.6. removed references to ot her voltages in note preceding table in section 4.6.6.
preface plx technology, inc. iv net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 preface the information contained in this document is subj ect to change without notice. this plx document to be periodically updated as new information is made available. scope this document describes the net2272 usb 2.0 pe ripheral controller operation and provides operational data for customer use. it also provid es functional details of the plx technology net2272 for hardware designers and software/firmware engineer s. this data book assumes that the reader has access to and is familiar with the documents referenced in th e following section. supplemental documentation usb implementers forum 5440 sw westgate drive #217, portland, or 97221 usa tel: 503 296-9892, fax: 503 297-1090, www.usb.org universal serial bus specification revision 2.0 ( usb r2.0 ) terminology term definition big endian most significant byte (msb) in a scalar is located at address 0. byte 8-bit data quantity. clock cycle one period of the internal 60-mhz clock. little endian least significant byte (lsb) in a scalar is located at address 0. local transaction read or write operation on th e local bus. includes an address phase, followed by one data transfer. local transfer during a transfer , data is moved from the source to the destination on the local bus. scalar multi-byte data element. target device that responds to a transa ction initiated by an external cpu or dma controller. word 16-bit data quantity.
net2272 local bus to usb 2.0 peripheral controller data book v copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 contents chapter 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2.1 usb transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2.2 serial interface engine (sie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2.3 usb protocol controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2.4 endpoint packet buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2.5 local bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2.6 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 net2272 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 connections to net2272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4.1 third-party part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4.2 general pcb layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4.2.1 usb differential signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4.2.2 analog vddc and vddio (power) . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4.2.3 analog vssc and vssio (ground) . . . . . . . . . . . . . . . . . . . . . . . 8 1.4.2.4 decoupling capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4.2.5 emi noise suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chapter 2 pin/ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 pin/ball description abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 pin/ball descriptions (tqfp and fbga packages) . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.1 digital power and ground pins/balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.2 usb transceiver pins/balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.3 clock, reset, and miscellaneous pins/balls . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.4 local bus pins/balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 physical pin/ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.1 64-pin plastic tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4.2 64-ball plastic fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 chapter 3 reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 reset# pin/ball . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 root-port reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 chapter 4 local bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 register addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.1 non-multiplexed direct address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.2 non-multiplexed indirect address mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.3 multiplexed address and data mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 control signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4 bus width and byte alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5 i/o transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5.1 non-multiplexed i/o write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5.2 multiplexed i/o write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5.3 non-multiplexed i/o read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
contents plx technology, inc. vi net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 4.5.4 multiplexed i/o read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.5 i/o performance at 3.3v vddio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.6 dma transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.6.1 dma write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.6.2 dma slow mode write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6.2.1 dma fast mode write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6.2.2 dma burst mode write timing . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.6.3 dma read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.6.3.1 dma slow mode read timing . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.6.3.2 dma fast mode read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.6.3.3 dma burst mode read timing . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.6.4 dma split bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.6.5 terminating dma transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.6.6 dma performance at 3.3v vddio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 chapter 5 usb functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 5.1 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 usb protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.1 tokens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.2 packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.3 transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.4 transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 automatic retries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.1 out transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.2 in transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4 ping flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.5 packet sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6 usb endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.6.1 control endpoint (endpoint 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.6.1.1 control write transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.6.1.2 control write transfer details . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.6.1.3 control read transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.6.1.4 control read transfer details . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.6.2 isochronous endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.6.2.1 isochronous out transactions . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.6.2.2 high-bandwidth isochronous out transactions . . . . . . . . . . . . 40 5.6.2.3 isochronous in transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.6.2.4 high-bandwidth isochronous in transactions . . . . . . . . . . . . . . 42 5.6.3 bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.6.3.1 bulk out transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.6.3.2 bulk in endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.6.4 interrupt endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.6.4.1 interrupt out transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.6.4.2 interrupt in endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.6.4.3 high-bandwidth interrupt endpoints . . . . . . . . . . . . . . . . . . . . . . 44 5.7 plx virtual endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.7.2 endpoint virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.7.3 efficiency considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.7.4 deadlock considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.7.5 buffer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
august, 2005 plx technology, inc. net2272 local bus to usb 2.0 peripheral controller data book vii copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 5.8 packet buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.8.1 out endpoint buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.8.2 in endpoint buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.8.2.1 16-bit post-validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.9 usb test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 chapter 6 interrupt and status register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2 interrupt status registers (irqstat0 and irqstat1) . . . . . . . . . . . . . . . . . . . . 51 6.3 endpoint response registers (ep_rspclr and ep_rspset) . . . . . . . . . . . . . 51 6.4 endpoint status register (ep_stat0 and ep_stat1) . . . . . . . . . . . . . . . . . . . . 51 chapter 7 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.2 usb low-power suspend state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.2.1 suspend sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.2.2 host-initiated wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.2.3 device-remote wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.2.4 resume interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.3 net2272 power configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.3.1 self-powered device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.4 net2272 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.4.1 usb suspend (unplugged from usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.4.2 power-on standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 chapter 8 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.2 register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.3 numeric register listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.4 main control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.5 usb control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8.6 endpoint registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.7 net2272 register differences from net2270 registers . . . . . . . . . . . . . . . . . . . 85 chapter 9 usb standard device requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.2 control write transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.3 control read transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.3.1 get other_speed_configuration descriptor . . . . . . . . . . . . . . . . . . . . . . . 92 9.3.2 get configuration descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 chapter 10 nand tree test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.1 nand tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.2 nand tree connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 chapter 11 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.3 dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.3.1 1.8v vddio core dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.3.2 2.5v vddio power supply requirements . . . . . . . . . . . . . . . . . . . . . . . 103 11.3.3 3.3v vddio power supply requirements . . . . . . . . . . . . . . . . . . . . . . . 105 11.3.4 usb full- and high-speed dc specifications . . . . . . . . . . . . . . . . . . . . 107 11.3.5 local bus dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
contents plx technology, inc. viii net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.4.1 usb full- and high-speed port ac specifications . . . . . . . . . . . . . . . . 109 11.4.2 usb full-speed port ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 11.4.3 usb port ac/dc specification notes . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.4.4 1.8v vddio local bus ac specifications . . . . . . . . . . . . . . . . . . . . . . . 113 11.4.4.1 1.8v vddio local bus non-multiplexed write . . . . . . . . . . . . 113 11.4.4.2 1.8v vddio local bus multiplexed write . . . . . . . . . . . . . . . . 114 11.4.4.3 1.8v vddio local bus non-multiplexed read . . . . . . . . . . . . 115 11.4.4.4 1.8v vddio local bus multiplexed read . . . . . . . . . . . . . . . . 116 11.4.4.5 1.8v vddio local bus dma write ? slow mode . . . . . . . . . . 117 11.4.4.6 1.8v vddio local bus dma write ? fast mode . . . . . . . . . . . 118 11.4.4.7 1.8v vddio local bus dma write ? burst mode . . . . . . . . . . 119 11.4.4.8 1.8v vddio local bus dma read ? slow mode . . . . . . . . . . 120 11.4.4.9 1.8v vddio local bus dma read ? fast mode . . . . . . . . . . 121 11.4.4.10 1.8v vddio local bus dma read ? burst mode . . . . . . . . . 122 11.4.5 2.5v vddio local bus ac specifications . . . . . . . . . . . . . . . . . . . . . . . 123 11.4.5.1 2.5v vddio local bus non-multiplexed write . . . . . . . . . . . . 123 11.4.5.2 2.5v vddio local bus multiplexed write . . . . . . . . . . . . . . . . 124 11.4.5.3 2.5v vddio local bus non-multiplexed read . . . . . . . . . . . . 125 11.4.5.4 2.5v vddio local bus multiplexed read . . . . . . . . . . . . . . . . 126 11.4.5.5 2.5v vddio local bus dma write ? slow mode . . . . . . . . . . 127 11.4.5.6 2.5v vddio local bus dma write ? fast mode . . . . . . . . . . . 128 11.4.5.7 2.5v vddio local bus dma write ? burst mode . . . . . . . . . . 129 11.4.5.8 2.5v vddio local bus dma read ? slow mode . . . . . . . . . . 130 11.4.5.9 2.5v vddio local bus dma read ? fast mode . . . . . . . . . . 131 11.4.5.10 2.5v vddio local bus dma read ? burst mode . . . . . . . . . 132 11.4.6 3.3v vddio local bus ac specifications . . . . . . . . . . . . . . . . . . . . . . . 133 11.4.6.1 3.3v vddio local bus non-multiplexed write . . . . . . . . . . . . 133 11.4.6.2 3.3v vddio local bus multiplexed write . . . . . . . . . . . . . . . . 134 11.4.6.3 3.3v vddio local bus non-multiplexed read . . . . . . . . . . . . 135 11.4.6.4 3.3v vddio local bus multiplexed read . . . . . . . . . . . . . . . . 136 11.4.6.5 3.3v vddio local bus dma write ? slow mode . . . . . . . . . . 137 11.4.6.6 3.3v vddio local bus dma write ? fast mode . . . . . . . . . . . 138 11.4.6.7 3.3v vddio local bus dma write ? burst mode . . . . . . . . . . 139 11.4.6.8 3.3v vddio local bus dma read ? slow mode . . . . . . . . . . 140 11.4.6.9 3.3v vddio local bus dma read ? fast mode . . . . . . . . . . 141 11.4.6.10 3.3v vddio local bus dma read ? burst mode . . . . . . . . . 142 chapter 12 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 12.1 64-pin plastic tqfp (10 x 10 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.2 64-ball plastic fbga (6 x 6 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 appendix a general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 a.1 product ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 a.2 united states and international representatives, and distributors . . . . . . . . . . . 145 a.3 technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
net2272 local bus to usb 2.0 peripheral controller data book ix copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 registers 11-1. (address 00h; regaddrptr) indirect register address pointe r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 11-2. (address 01h; regdata) indirect regi ster data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11-3. (address 02h; irqstat0) inte rrupt status (low byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11-4. (address 03h; irqstat1) in terrupt status (high byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11-5. (address 04h; pagesel) endpoint page select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11-6. (address 1ch; dmareq) dma request control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11-7. (address 1dh; scratch) scratchpad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11-8. (address 20h; irqenb0) interrupt enab le (low byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11-9. (address 21h; irqenb1) interrupt enab le (high byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11-10. (address 22h; locctl) local bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11-11. (address 23h; chiprev_legacy) legacy silicon revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 11-12. (address 24h; locctl1) local bus control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11-13. (address 25h; chiprev_2272) net2272 silicon revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 11-14. (address 18h; usbctl0) usb control (low byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11-15. (address 19h; usbctl1) usb control (high byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11-16. (address 1ah; frame0) frame counter (low byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11-17. (address 1bh; frame1) frame counter (high byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11-18. (address 30h; ouraddr) our current usb address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11-19. (address 31h; usbdiag) usb diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 11-20. (address 32h; usbtest) usb test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11-21. (address 33h; xcvrdiag) transceiver diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11-22. (address 34h; virtout0) virtual out interrupt 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11-23. (address 35h; virtout1) virtual out interrupt 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11-24. (address 36h; virtin0) virtual in interrupt 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11-25. (address 37h; virtin1) virtual in interrupt 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 11-26. (address 40h; setup0) setup byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11-27. (address 41h; setup1) setup byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11-28. (address 42h; setup2) setup byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11-29. (address 43h; setup3) setup byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11-30. (address 44h; setup4) setup byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11-31. (address 45h; setup5) setup byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11-32. (address 46h; setup6) setup byte 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11-33. (address 47h; setup7) setup byte 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11-34. (address 05h; ep_data) endpoint data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11-35. (address 06h; ep_stat0) endpoint status (low byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 11-36. (address 07h; ep_stat1) endpoint status (high byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11-37. (address 08h; ep_transfer0) in endpoint transfer count (byte 0) . . . . . . . . . . . . . . . . . . . . . . . . . 78 11-38. (address 09h; ep_transfer1) in endpoint transfer count (byte 1) . . . . . . . . . . . . . . . . . . . . . . . . . 79 11-39. (address 0ah; ep_transfer2) in endp oint transfer count (byte 2) . . . . . . . . . . . . . . . . . . . . . . . . . 79 11-40. (address 0bh; ep_irqenb) endpoint interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 11-41. (address 0ch; ep_avail0) endpoint available count (low byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0 11-42. (address 0dh; ep_avail1) endpoint available count (high byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0 11-43. (address 0eh; ep_rspclr) endpoint response clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 11-44. (address 0fh; ep_r spset) endpoint response set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11-45. (address 28h; ep_maxpkt0) endpoint maximum packet size (low byte) . . . . . . . . . . . . . . . . . . . . . . 82 11-46. (address 29h; ep_maxpkt1) endpoint maximum packet size (high byte) . . . . . . . . . . . . . . . . . . . . . . 82 11-47. (address 2ah; ep_cfg) endpoint configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11-48. (address 2bh; ep_hbw) endpoint high bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11-49. (address 2ch; ep_buff_states) endpoi nt buffer states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

net2272 local bus to usb 2.0 peripheral controller data book 1 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 chapter 1 introduction 1.1 features ? universal serial bus specification r2.0 ( usb r2.0 ) compliant usb full (12 mbps) and high (480 mbps) speeds three configurable physical endpoints, in addition to endpoint 0 supports 30 configurable virtual endpoints configurable endpoints can be isochronous, bulk, or interrupt, as well as in or out high-bandwidth isochronous mode maximum packet size up to 1 kb, double-buffered internal 3-kb memory provides transmit and receive buffers local cpu bus easily interfaces to generic cpus 8- or 16-bit cpu or dma bus transfers optional dma split bu s mode, with dedicated dma and cpu access multiple register address modes support direct and indirect register addressing automatic retry of failed packets diagnostic register allo ws forced usb errors software-controlled disconnect allows re-enumeration atomic operation to set and clear status bits simplifies software 30-mhz oscillator with internal phase-locked loop (pll) multiplier output clock to local bus ? eight programmable frequencies, from off to 60 mhz 1.8v, 2.5v, and 3.3v operating voltages, 5v tolerant i/o low-power cmos technology in 64-pin plastic tqfp or 64-ball fbga package lead-free and rohs (reduction of hazardous substances) compliant 1.2 overview the net2272 usb peripheral controller allows control , isochronous , bulk , and interrupt transfers between a local bus and universal serial bus (usb ). the net2272 supports the device side of a connection between a usb host comput er and intelligent peripherals, such as printers, image scanners, and digital cameras. the six main modules are as follows: usb transceiver serial interface engine (sie) usb protocol controller endpoint packet buffers local bus interface configuration registers each module is briefly described in the sections that follow.
introduction plx technology, inc. 2 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 1.2.1 usb transceiver supports full- (12 mbps) or high-speed (480 mbps) operation serial data transmitter and receiver parallel data interface to se rial interface engine (sie) single parallel data clock output with on-chip pll to generate high-speed serial data clocks data and clock recovery from usb serial data stream sync/end-of-packet (sync/eop) generation and checking bit-stuffing/unstuffing; bit-stuff error detection logic to facilitate resume signaling logic to facilitate wakeup and suspend detection ability to switch between full- and high-speed terminations and signaling 1.2.2 serial interface engine (sie) interface between packet buffers and usb transceiver crc generator and checker packet identifier (pid) decoder forced error conditions usb r2.0 test modes 1.2.3 usb protocol controller host-to-device communication automatic retry of failed packets up to three isochronous, bulk, or interrupt endp oints, each with a configurable packet buffer supports up to 30 virtual endpoints, with the ability to be mapped to physical endpoints configurable control endpoint 0 interface to packet buffers software-controlled disconnect signaling allows device re-enumeration software-controlled usb suspend and root-port reset detection software-controlled device-remote wakeup software-controlled root-port wakeup 1.2.4 endpoint packet buffers choice of four preset configurations to simplify programming separate 128-byte packet bu ffer for physical endpoint 0 3 kb of configurable packet buffer memory for physical endpoints a, b, and c maximum packet size up to 1 kb, double-buffered
august, 2005 local bus interface net2272 local bus to usb 2.0 peripheral controller data book 3 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 1.2.5 local bus interface target interfaces to 8- or 16-bit cpu access to internal transmit and receive packet buffers dma split bus transactions (dma and cpu on separate data buses) dma burst mode supports dma and interrupt transfers optional multiplexed address/data bus, using ale for low pin/ball-count applications indirect addressing, allowi ng access to all registers with only a single address bit 1.8v, 2.5v, and 3.3v operating voltages, 5v tolerant i/o 1.2.6 configuration registers internal registers acce ssible from local bus main control registers for common functions usb control registers for usb protocol controller module control registers for each endpoint
introduction plx technology, inc. 4 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 1.3 net2272 block diagrams figure 1-1. net2272 block diagram usb endpoint buffer manager memory controller utmi usb2.0 sie usb protocol controller cpu interface controller internal bus master pll configuration registers rpu rsdp dp dm rsdm rref oscillator xin xout vdd25 vdd33 pvdd avdd internal clock com gnd avss internal ram power / clock manager reset# internal reset suspend control vddc vssc vddio vssio control logic digital core supply i/o pad supply 6 2 5 16 12, 14 4, 10 15 11 7 3 13 9 8 57 58 26 25 lclko 64 vbus 1, 48 24, 56 27, 42, 55 33, 41, 54 63 dma interface handler main usb ep split-bus dma la[4:0] ale iow# ior# cs# irq# dmard# dack dreq dmawr# eot ld[15:0] 59 61 34 50 52 51 62 28-32 60 53 49, 47-43 39-35, 23-19 tmc2 test trst 17 18 40 test controller test logic
august, 2005 net2272 block diagrams net2272 local bus to usb 2.0 peripheral controller data book 5 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 figure 1-2. cpu-based de vice controller diagram figure 1-3. asic with dma split bus diagram net2272 usb controller usb connector usb cable cpu rom ram cpu-based device controller application interface dma net2272 usb controller usb connector usb cable asic (with embedded dma) cpu rom ram split bus dma
introduction plx technology, inc. 6 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 1.4 connections to net2272 figure 1-4. sample connections to net2272 2.5_vcc c10 0.1uf 1 2 2.5_vcca ale reset# ior# cs# dack eot c tp1 1 clock_out usblgnd 3.3vcc c6 0.1uf 1 2 3.3vcc dreq vio irq# + c14 10uf 1 2 r9 169k 1% r8 174k 1% r1 1k 1 2 vio r3 39.2 +/- 1% 1 2 r2 39.2 +/- 1% 1 2 vbusl u1 n2272 la0 32 la1 31 la2 30 la3 29 la4 28 cs# 61 ior# 59 iow# 60 ale 53 dmawr# 34 reset# 58 dack 51 eot 52 test 18 tr st 40 xi n 25 xo u t 26 rref 13 vbus 64 ld0 19 ld1 20 ld2 21 ld3 22 ld4 23 ld5 35 ld6 36 ld7 37 ld8 38 ld9 39 ld10 43 ld11 44 ld12 45 ld13 46 ld14 47 ld15 49 dreq 62 irq# 63 lclko 57 vddc1 1 vdd33 7 avdd 15 vddio3 55 vdd25 3 vddc2 48 vddio1 27 vssc1 24 vssc2 56 vssio1 33 vssio2 41 gnd2 4 gnd1 10 avss1 12 avss2 14 com 16 tmc 2 17 dmard# 50 pvdd 11 vddio2 42 vssio3 54 rsdm 9 dm 8 dp 6 rsdp 5 rpu 2 iow# dmawr# r4 1.5k 1 2 d1 pgb0603 1 2 usbvcc pin5 of j1 is the shield of the usb type b connector + c5 10uf 1 2 + c4 10uf 1 2 c7 0.01uf 1 2 c8 0.1uf 1 2 c9 0.01uf 1 2 2.5_vcc u2 tps76301 vin 1 vout 5 gnd 2 fb 4 en 3 c13 0.1uf 1 2 c15 0.1uf 1 2 3.3vcc c16 0.01uf 1 2 c17 0.1uf 1 2 c18 0.01uf 1 2 c11 0.01uf 1 2 j1 usb_b 1 1 2 2 3 3 4 4 gnd 5 + c12 10uf 1 2 c3 0.01uf 1 2 r5 1m 1 2 usbcgnd 2.5_vcc l3 1uh 1 2 rref 2.5_vcca 2.5_vcca vio 2.5_vcc la2 la1 la4 la3 la5 r7 47k 1 2 r6 2.43k +/- 1% 1 2 note: for 16-bit bus, use address bits 5:1; for 8-bit bus, use address bits 4:0. l4 1uh 1 2 analog ground digit al ground c2 10pf 1 2 c1 10pf 1 2 y1 30 mhz 1 2 ld0 ld4 ld5 ld1 ld3 ld2 ld7 ld6 ld8 ld13 ld14 ld9 ld15 ld12 ld11 ld10 la[5:1] dmard# ld[15:0]
august, 2005 third-party part numbers net2272 local bus to usb 2.0 peripheral controller data book 7 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 1.4.1 third-party part numbers note: the crystal should maintain a tolerance of 0.01% (100 ppm) to guarantee a 480 mbps 500 ppm data rate. 1.4.2 general pcb layout guidelines the usb r2.0 high-speed 480 mbps data transfers utilize 400 mv differential sign aling. this requires special printed circuit board (pcb) layout requirements. (refer to the intel u sb layout guidelines .) warning: the following guidelines must be observed to ensure proper net2272 operation. it is strongly recommended that schema tics and pcb layout be submitted to plx technical support for review prior to pcb fabrication. 1.4.2.1 usb differential signals consult with board manufacturer to determine la yer separation, trace width, and trace separation for maintaining 90-ohm differential impedance. maintain equal trace lengths for d+ and d-. minimize number of vias and curves on d+ and d- traces. use two 45 turns, instead of one 90 turn. minimize trace lengths shown in bold in the schematic provided in figure 1-4 . prevent d+ and d- traces from crossing a power-plane void. the same ground layer to remain next to the d+ and d- traces. place digital ground (vssc and vssio) layer next to the layer where d+ and d- are routed. avoid using stubs or test points for observing usb signals. maximize the distance of d+ and d- from other signals, to prevent crosstalk. 1.4.2.2 analog vddc and vddio (power) analog power must be filtered from the digital power, using the provided example circuit ( figure 1-4 ). analog and digital vddc and vddio must be connected by way of a 1 h inductor. analog vddc and vddio must be separated from digital vddc and vddio. if analog and digital vddc and vddio are in the same layer, split the layer to accommodate the two power signals. connect the avdd and pvdd pins/balls to analog vddc and vddio. table 1-1. third-party part numbers part manufacturer part number website 30 mhz fundamental crystal (y1) kds daishinku corp. at-49 30.000-16 w ww.kdsj.co.jp/english.html 1 h inductor, 10%, 0805 package (l3-l4) taiyo yuden lk21251r0k w ww.t-yuden.com/inductors/index.cfm esd suppressor, 0603 package (d1) littelfuse pgb0010603mr w ww.littelfuse.com/data/en/data_sheets/ pgb0603.pdf 2.43k, 1% resistor, 0.1w, 0603 package (r6) panasonic erj6enf2431v w ww.panasonic.com/industrial/components/pdf/ 002_er13_erj_2r_3r_6r_3e _6e_8e_14_12_dne.pdf usb b connector newnex urb-1001 w ww.newnex.com
introduction plx technology, inc. 8 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 1.4.2.3 analog vssc and vssio (ground) analog ground must be filtered from the digital ground, using the provided example circuit ( figure 1-4 ). analog and digital vssc and vssio must be connected by way of a 1 h inductor. connect the avss and com pins/balls and the rref pin/ball?s resistor to analog vssc and vssio. 1.4.2.4 decoupling capacitors for every two pairs of digital/analog vddc and vddio and vssc and vssio, locate at least one 0.1 f and one 0.01 f decoupling capacitor near the net2272 device. decoupling capacitors can be placed on either side of the pcb. provide at least one 10 f decoupling capacitor for every five 0.1 f or 0.01 f decoupling capacitors. use capacitors with good quality at high frequency for low equivalent series resistance (esr), such as tantalum or ceramic capacitors. do not use electrolytic capacitors. 1.4.2.5 emi noise suppression a common-mode choke coil can effectively supp ress electromagnetic interference (emi) noise, although such a coil can affect the usb r2.0 signal quality. use a good quality noise filter, if necessary. for typical implementation, a choke is not required. use quality, shielded cables.
net2272 local bus to usb 2.0 peripheral controller data book 9 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 chapter 2 pin/ball description 2.1 pin/ball description abbreviations note: input pins/balls that do not have an internal pu ll-up nor pull-down resistor must be externally driven when the net2272 is in the low-power suspend state. 2.2 packaging information for net2272 packaging information, refer to chapter 12, ?mechanical specifications.? table 2-1. pin/ball d escription abbreviations abbreviation description i input o output i/o bi-directional s schmitt trigger ts three-state tp totem pole od open drain #active low
pin/ball description plx technology, inc. 10 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 2.3 pin/ball descriptions (tqfp and fbga packages) 2.3.1 digital power and ground pins/balls table 2-2. digital power and ground (10 pins/balls) signal name pins/balls type description tqfp fbga vddc 1, 48 a7, h8 power digital core supply voltage connect to 2.5v supply. vddio 27, 42, 55 d7, e3, f5 power i/o interface supply voltage connect to voltage be tween 1.8v and 3.3v. vssc 24, 56 d2, d8 ground digital core ground connect to ground. vssio 33, 41, 54 f8, h1, h4 ground i/o interface ground connect to ground.
august, 2005 usb transceiver pins/balls net2272 local bus to usb 2.0 peripheral controller data book 11 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 2.3.2 usb transceiver pins/balls table 2-3. usb transceiver (15 pins/balls) signal name pins/balls type description tqfp fbga avdd 15 c3 power analog supply voltage connect to analog 2.5v supply. avss 12, 14 b2, b6 ground analog ground connect to analog ground. com (avss) 16 a2 ground pll ground connect to analog ground. dm 8 b3 i/o high-speed usb negative data port dm is the high-speed negative differ ential data signal of the usb data port. dm also acts as the full-spe ed negative differential input data port. dm connects directly to the usb connector. dp 6 b5 i/o high-speed usb positive data port dp is the high-speed positive differential data signal of the usb data port. dp also acts as the full-speed positive differential input data port. dp connects dire ctly to the usb connector. gnd 4, 10 a4, a6 ground digital ground connect to ground. pv dd 11 c4 power pll supply voltage connect to analog 2.5v supply. rpu 2 d5 o dp pull-up resistor connect to the dp pin/ball through a 1.5k-ohm resistor. rref 13 d4 i reference resistor connect 2.43k-ohm 1% resistor to analog ground. typical voltage on this pin/ball is 1.27v. rsdm 9 a3 o full-speed usb negative output data port rsdm is the full-speed negative differential output data signal of the usb data port. connect th rough a 39.2-ohm 1% resistor to the usb connector. rsdp 5 a5 o full-speed usb positive output data port rsdp is the full-speed positive differential output data signal of the usb data port. connect th rough a 39.2-ohm 1% resistor to the usb connector. vdd25 3 c5 power supply voltage connect to digital 2.5v supply. vdd33 7 b4 power supply voltage connect to digital 3.3v supply.
pin/ball description plx technology, inc. 12 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 2.3.3 clock, reset, and miscellaneous pins/balls table 2-4. clock, reset, and miscellaneous (8 pins/balls) signal name pins/balls type description tqfp fbga lclko 57 e6 o 12 ma ts local clock output buffered clock output from the in ternal pll, with the frequency depending on the locctl register local clock output field state. lclko stops osc illating when the net2272 is placed in the low-power suspend state. lclko is not driven while the net2272 is suspended. when the internal oscillat or is started, lclko is prevented from driving for 2 ms. lclko does not oscillate while the net2272 in power-down mode. reset# 58 c6 i s external reset connect to local or power-on reset. to reset when the oscillator is stopped (initial power-up or in the low-power suspend state), assert for at least 2 ms. when oscillator is running, assert for at least five 60-mhz clock periods. test 18 e4 i test input connect to ground for normal operation. to enable nand tree, set test and la[4:3] high. (refer to chapter 10, ?nand tree test ,? for further details.) tmc2 17 e5 i tmc2 test input. i/o buffer control connect to ground for normal operation. trst 40 g5 i trst test input. test access port (tap) controller reset connect to ground for normal operation. vbus 64 b8 i s usb vbus vbus indicates when th e net2272 is connected to a powered-up usb host connector. c onnect a 47k-ohm pull-down re sistor to vbus to hold vbus low when not connected to the usb. xin 25 e1 i oscillator input connect to 30-mhz crystal or external oscillator module. xout 26 d1 o oscillator output connect to crystal, or leave open wh en using an external oscillator module. the oscillator stops when the net2272 is in the low-power suspend state.
august, 2005 local bus pins/balls net2272 local bus to usb 2.0 peripheral controller data book 13 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 2.3.4 local bus pins/balls table 2-5. local bus (31 pins/balls) signal name pins/balls type description tqfp fbga ale 53 e8 i address latch enable when operating in multiplexed a ddress and data mode, the 5-bit address bus is latched on the traili ng (negative) edge of ale. the net2272 automatically detects ale use to indicate multiplexed address and data use on the ld[4:0] pins/balls. connect to ground when operating in non-multiplexed register addressing modes. cs# 61 c7 i chip select cs# enables access to registers w ithin the net2272. asserting cs# during the low-power suspend state wakes up the net2272. asserting cs# during reset# holds the net2272 in the low-power suspend state by disabling the internal oscillator. dack 51 f7 i dma acknowledge dack is used to transfer data to and from the packet buffer in response to dreq. dack is ignored unless the locctl1 register dma dack enable bit is set. dack polarity is programmable. dmard# 50 g7 i dma read strobe the dma bus master asserts dmard# during a dma read transaction when dma split bus mode is selected dmawr# 34 h3 i dma write strobe the dma bus master asserts dmawr# during a dma write transaction when dma split bus mode is selected. dreq 62 a8 o 3 ma ts dma request dreq requests dma transfers from an external dma controller. dreq floats when the usb host suspends the net2272. dreq polarity is programmable. eot 52 e7 i end of transfer eot (from an external dma controller) is used to terminate a dma transfer. the current word is transferred; however, no additional transfers are reque sted. eot can be programmed to cause an interrupt. eot polarity is programmable. ior# 59 c8 i read strobe the local bus master asserts ior# during a read transaction. iow# 60 b7 i write strobe the local bus master asserts iow# during a write transaction.
pin/ball description plx technology, inc. 14 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 irq# 63 d6 o 12 ma od interrupt request output irq# interrupts the local processor, based on events selected in the internal program registers. becaus e irq# is an open-drain pin/ball, an external 1k-ohm pull-up resistor is required. la[4:0] 28, 29, 30, 31, 32 f1, e2, f2, g2, g1 i address bus five address bits can directly address most net2272 internal registers (non-multiplexed dire ct address mode). a minimum of one address bit is required to operate the net2272, using an optional register non-multip lexed indirect address mode. a third addressing mode (multipl exed address and data) uses ale with ld[4:0] to provide five bits of register addressing. (refer to chapter 4, ?local bus interface ,? for further details.) to enable nand tree, se t la[4:3] and test high. (refer to chapter 10, ?nand tree test ,? for further details.) ld[15:0] 49, 47, 46, 45, 44, 43, 39, 38, 37, 36, 35, 23, 22, 21, 20, 19 g8, h7, h6, f6, h5, g6, f4, g4, f3, g3, h2, d3, c1, c2, b1, a1 i/o 6 ma data bus ld[15:0] serve as the local cpu i/o data bus. in multiplexed address and data mode, ale can be used with ld[4:0] to provide five address bits on the falling edge of ale. in 16-bit mode, the data bus is 16 bits wide. (refer to section 4.2.3, ?multiplexed address and data mode,? for further details.) table 2-5. local bus (31 pins/balls) (cont.) signal name pins/balls type description tqfp fbga
august, 2005 physical pin/ball assignment net2272 local bus to usb 2.0 peripheral controller data book 15 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 2.4 physical pin/ball assignment 2.4.1 64-pin plastic tqfp figure 2-1. physical pin assignment (64-pin plastic tqfp package) note: this drawing is for informational purposes only. contact plx for additional chip marking, pcb layout, and manufacturing information. net2272 xxxxxxx revx 1 17 32 33 49 64 50 51 52 53 54 55 56 57 58 59 60 61 62 63 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 vddc rpu vdd25 gnd rsdp dp vdd33 dm rsdm gnd pvdd avss rref avss avdd com test ld0 ld1 ld2 ld3 ld4 vssc xin xout vddio la4 la3 la2 la1 la0 tmc2 vssio dmawr# ld5 ld6 ld7 ld8 ld9 trst vssio vddio ld10 ld11 ld12 ld13 ld14 vddc ld15 dmard# dack eot ale vssio vddio vssc lclko reset# ior# iow# cs# dreq irq# vbus
pin/ball description plx technology, inc. 16 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 2.4.2 64-ball plastic fbga figure 2-2. physical ball assignment (64-ball plastic fbga package, underside view) note: this drawing is for informational purposes only. contact plx for additional chip marking, pcb layout, and manufacturing information.
net2272 local bus to usb 2.0 peripheral controller data book 17 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 chapter 3 reset and initialization 3.1 overview the net2272 normal initialization sequence consists of the following: 1. the net2272 reset# signal is asserted and de-asserted. 2. local cpu initializes usb and lo cal bus configuration registers. 3.2 reset# pin/ball the reset# pin/ball resets all net2272 logic to its default state. reset# is typically connected to a power-on reset circuit. 3.3 root-port reset if the net2272 detects a single-ended zero on the root port for greater than 2. 5 s, the single-ended zero is interpreted as a root-port reset. root-port reset is recognized only when the vbus input pin/ball is high, and the usbctl0 register usb detect enable bit is set. the following resources are reset: sie usb state machines local state machines ouraddr register buffer pointers root-port reset does not affect the remainder of the configuration registers. the root-port reset interrupt bit is set when a root-port reset is detect ed. the local cpu takes appropriate action when this interrupt occurs. according to the usb r2.0 , the usb reset width is minimally 10 ms and can be longer, depending on the upstream host or hub. there is no specified maximum usb reset width.
reset and initialization plx technology, inc. 18 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 3.4 reset summary table 3-1 delineates which device resources are reset when either of the two reset sources are asserted. table 3-1. reset summary reset sources device resources usb, sie modules, ouraddr register all configuration registers endpoint buffer pointers reset# x x x usb root-port reset x ? x
net2272 local bus to usb 2.0 peripheral controller data book 19 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 chapter 4 local bus interface 4.1 overview the local bus interface allows the net2272 to easi ly interface with many generic processors and custom asic interfaces. both multiplexed and non-multiplexed buses are supported. 4.2 register addressing modes the net2272 provides thr ee register addressing modes that support various user architectures: non-multiplexed direct address mode non-multiplexed indirect address mode multiplexed address and data mode these addressing modes always remain active and no sp ecial effort is required to use them. the modes act on a transaction-by-transaction basis, allowing dma and cpu to operate wi th inherently differing bus architectures. for example , the cpu can operate with a multiplexed bus (using ale to de-multiplex the address/data bus), while dma can op erate using a non-multiplexed data bus. 4.2.1 non-multiplexed direct address mode non-multiplexed direct address mode uses la[4:0 ] to directly access the first 32 configuration registers. 4.2.2 non-multiplexed indirect address mode non-multiplexed indirect address mode uses the regaddrptr and regdata registers (addresses 00h and 01h, respectively) to provid e a command/data interface to the net2272 internal registers and buffers. all cpu transactions performed with regdata have their address sourced by regaddrptr . the local cpu first programs regaddrptr with the needed register address, then reads or writes to regdata with the data intended for the register pointed to by regaddrptr . this addressing mode requires only one physical address bit (to access address 00h or 01h). all net2272 unused address bits must be c onnected to ground. when a ll five address bits are being used, this addressing mode allows access to registers above address 1fh. 4.2.3 multiplexed address and data mode multiplexed address and data mode uses the ale pin/ball to de-multiplex data bus addresses. the net2272 automatically detects ale use, and utilizes the address repr esented by ld[4:0] on the falling edge of ale as the current transaction address. th is addressing mode is supported by several common microcontrollers. ale is grounded when this mode is not used.
local bus interface plx technology, inc. 20 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 4.3 control signal definitions control signals direct the flow of data across the local bus. a write transaction is performed by asserting cs# and iow#. the address and data must be valid on the trailing (rising) edge of iow#. a read transaction is performed by asserting cs# and ior#. 4.4 bus width and byte alignment the local bus supports 8- or 16-bit buses. in 8-b it mode, all configuration registers and buffers are accessed one byte at a time. a typical 8-bit applicat ion connects the cpu addre ss bits a[4:0] to the net2272 address bus la[4:0]. in 16-bit mode, the confi guration registers remain accessed one byte at a time; however, the buffers are accessed one word at a time. the locctl configuration register byte swap bit determines whether the bytes are swapped as they are written into the bu ffer in 16-bit mode. this allows for connections to little or big endian processors. a typical 16-bit application connects the cpu address bits a[5:1] to the net2272 address bus la[4:0].
august, 2005 i/o transactions net2272 local bus to usb 2.0 peripheral controller data book 21 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 4.5 i/o transactions i/o transactions are those in which a cpu on the local bus accesse s registers or packet buffers within the net2272. 4.5.1 non-multiplexed i/o write non-multiplexed i/o writes begin when both cs# and iow# are asserted. the address and write data must meet the setup time, with respect to the write transaction end. data is written into the register or packet buffer when cs# or iow# is de-asserted. a new i/o write transaction cannot start until the t15a recovery time expires, and a new i/o read tr ansaction cannot start unti l the t15b recovery time expires. ale must be held low for non-multiplexed mode. note: for 1.8, 2.5, and 3.3v vddio setup and t timing values, refer to table 11-29 , table 11-39 , and table 11-49 , respectively. figure 4-1. non-multiplexed i/o write timing 4.5.2 multiplexed i/o write multiplexed i/o write transactions ar e started when the address is driv en onto the lower bits of the data bus, and ale is pulsed. after the address is latche d into the net2272, the data phase is initiated with cs# and iow# assertion. the write data must meet the setup time, wi th respect to the write cycle end. data is written into the register or packet buff er when cs# or iow# is de-asserted. a new i/o write transaction cannot start until the t15a recovery ti me expires, and a new i/o read transaction cannot start until the t15b recovery time expires. note: for 1.8, 2.5, and 3.3v vddio setup and t timing values, refer to table 11-30 , table 11-40 , and table 11-50 , respectively. figure 4-2. multiplexed i/o write timing a0 a1 d0 d1 0ns 10ns 20ns 30ns 40ns 50ns la[4:0] ld[15:0] cs# iow# d0 d1 a0 a1 0ns 10ns 20ns 30ns 40ns 50ns 60ns ale ld[15:0] cs# iow#
local bus interface plx technology, inc. 22 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 4.5.3 non-multiplexed i/o read non-multiplexed i/o read transactions are started when both cs# and ior# are asserted. the address must be valid t4 before cs# and ior# are both asserted. valid read data is driven onto the data bus within t6 after cs# and ior# ar e both asserted. the read transac tion ends and the data bus floats when cs# or ior# is de-asserted. a new i/o read transaction cannot start until the t8a recovery time expires, and a new i/o write trans action cannot start until the t8b recovery time expires. ale must be held low for non-multiplexed mode. note: for 1.8, 2.5, and 3.3v vddio t timing values, refer to table 11-31 , table 11-41 , and table 11-51 , respectively. figure 4-3. non-multiplexed i/o read timing 4.5.4 multiplexed i/o read multiplexed i/o read transactions are started when th e address is driven onto the lower bits of the data bus, and ale is pulsed. after the address is latched into the net2272, the data phase is initiated with cs# and ior# assertion. to pr event data bus contention, do not assert cs# and ior# until the local bus master has three-stated the addre ss. valid read data is driven onto the data bus within t6 after cs# and ior# are both asserted. the read transaction e nds and the data bus floats when cs# or ior# is de-asserted. a new i/o read trans action cannot start until the t8a recovery time expires, and a new i/o write transaction cannot start until the t8b recovery time expires. note: for 1.8, 2.5, and 3.3v vddio t timing values, refer to table 11-32 , table 11-42 , and table 11-52 , respectively. figure 4-4. multiplexed i/o read timing a0 d0 a1 d1 0ns 25ns 50ns 75ns la[4:0] cs# ior# ld[15:0] d0 d1 a0 a1 0ns 25ns 50ns 75ns 100ns ale cs# ior# ld[15:0]
august, 2005 i/o performance at 3.3v vddio net2272 local bus to usb 2.0 peripheral controller data book 23 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 4.5.5 i/o performance at 3.3v vddio table 4-1 delineates i/o performance specifications at 3.3v vddio. note: for t timing values, refer to table 11-49 through table 11-52 . table 4-1. i/o performance specifications at 3.3v vddio transaction type specification value non-multiplexed write write width (t12) 5 ns write to write recovery time (t15a) 28 ns 8-bit bus maximum performance 1/33 ns = 30 mb/s 16-bit bus maximum performance 2/33 ns = 60 mb/s multiplexed write ale width (t3) 5 ns ale to write command (t19) 1 ns minimum write width (t12) 5 ns write to write recovery time (t15a) 28 ns 8-bit bus maximum performance 1/39 ns = 25 mb/s 16-bit bus maximum performance 2/39 ns = 50 mb/s non-multiplexed read read access time (t6) 18 ns read recovery time (t8) 19 ns 8-bit bus maximum performance 1/37 ns = 27 mb/s 16-bit bus maximum performance 2/37 ns = 54 mb/s multiplexed read ale width (t3) 5 ns ale to read command (t19) 1 ns minimum read access time (t6) 18 ns read recovery time (t8) 19 ns 8-bit bus maximum performance 1/43 ns = 23 mb/s 16-bit bus maximum performance 2/43 ns = 46 mb/s
local bus interface plx technology, inc. 24 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 4.6 dma transactions dma transfers are those in which an external dma controller transfers data between memory and one of the packet buffers within the net2272. dma transfers can be configured only for endpoint a or b. the local cpu handles transfers to and from endp oints 0 and c. the external dma controller is programmed to perform fly-by demand mode transfer s. in fly-by demand mo de, transfers occur only when the net2272 requests them. the data is transferred between the net2272 and local memory during the same bus transaction. during dma transactions, the endpoi nt buffer is determined by the dmareq register dma endpoint select field. during cpu transactions, the endpoint buffer is determined by the pagesel register page select field. in dma split bus mode, cpu accesses to an endpoint buffer can simultaneously occur with dma accesses to another endpoint buffer. 4.6.1 dma write for in transfers (net2272-to-host), the local and ho st cpus first arrange to transfer a block of data from local memory to host memory . the local cpu programs the exte rnal dma controller to transfer the needed number of bytes. the net2272 ep_transfer x registers are also programmed with the needed transfer size (in bytes). th e transfer size programmed into the ep_transfer x registers can span many packets, allowing a single dma setup to transfer multiple packet s. the dma request signal (dreq) is asserted whenever buff er space is available. the endpoint maximum packet size register controls the maximum number of bytes transmitted to the host in a single packet. a short packet is transmitted if bytes remain to transfer after all ep_transfer x bytes are written, or when eot is asserted during the last dma cycle and the dmareq register dma buffer valid bit is set. the dreq, dack, iow#, and eot signals control tr ansactions between the external dma controller and net2272. dreq and dack are minimally needed to exchange data with the net2272, because the direction (write) is established by the ep_cfg register endpoint direction bit. the operation mode is set by the dmareq register dma control dack bit. if the dma control dack bit is high, the net2272 needs dack and iow# for a dma write. if the bit is low, only dack is needed for a dma write. the local cpu programs the net2272 dmareq register to associate the dma dreq and dack signals with a net2272 endpoint (endpoint a or b). transfers occur only when the net2272 requests them, after the dmareq register dma request enable bit is set. if space is available in the selected endpoint bu ffer, and bytes remaining to transfer, the net2272 requests dma transfers by asserting dreq. the ex ternal dma controller then requests the local bus from the local cpu. after the dma controller is granted the bus, the controller drives dack, iow# (optional), and external dma controller memr# out put (to memory) to transfer one byte from memory to the endpoint buffer. for dma slow mode, the net2272 de-asserts dreq within t20 after the transaction starts. for dma fast mode, the net227 2 de-asserts dreq when the transaction starts. if there is buffer space available and remaining by tes to transfer, the net2272 re-asserts dreq. the usb host transmits an in token to the net2272 an d starts an in data transaction from the selected endpoint buffer. dma transfers continue until the number of bytes specified by ep_transfer x are transferred, or eot is asserted.
august, 2005 dma write net2272 local bus to usb 2.0 peripheral controller data book 25 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 the irqstat0 register dma done interrupt bit is set for the following conditions: eot is asserted during the last dma transfer ep_transfer x counter counts down to 0 local cpu writes a 0 to the ep_transfer x register after the dma transfer is complete when dma burst mode is selected, dreq is asserted when buffer space is available and the dma request enable bit is set. dreq remains asserted until one of the following conditions is met: buffer becomes full dma request enable bit is cleared ep_transfer x counter counts down to 0 eot is asserted
local bus interface plx technology, inc. 26 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 4.6.2 dma slow mode write timing for dma slow mode write timing, dreq is de-asserted within t20 after the write transaction starts. dreq is re-asserted within t21 after the write transaction ends. note: for 1.8, 2.5, and 3.3v vddio t timing values, refer to table 11-33 , table 11-43 , and table 11-53 , respectively. figure 4-5. dma slow mode write timing 4.6.2.1 dma fast mode write timing in dma fast mode write timing, dreq is de-asserted when the write transaction starts. dreq is re-asserted within t21 after the write transaction ends. note: for 1.8, 2.5, and 3.3v vddio t timing values, refer to table 11-34 , table 11-44 , and table 11-54 , respectively. figure 4-6. dma fast mode write timing d0 d1 0ns 25ns 50ns 75ns 100ns 125ns dreq ld[15:0] dack# iow# (optional) eot# (optional) d0 d2 d1 0ns 25ns 50ns 75ns 100ns dreq ld[15:0] dack# iow# (optional) eot# (optional)
august, 2005 dma slow mode write timing net2272 local bus to usb 2.0 peripheral controller data book 27 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 4.6.2.2 dma burst mode write timing in dma burst mode write timing, dreq remains asserted until the dma transfer completes. note: for 1.8, 2.5, and 3.3v vddio t timing values, refer to table 11-35 , table 11-45 , and table 11-55 , respectively. figure 4-7. dma burst mode write timing d0 d2 d1 0ns 25ns 50ns 75ns 100ns dreq ld[15:0] dack# iow# (optional) eot# (optional)
local bus interface plx technology, inc. 28 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 4.6.3 dma read for out transfers (host-to-net2272), the local and host cpus first arrange to transfer a block of data from host memory to local memory. the local cpu programs the external dm a controller to transfer the needed number of bytes. the dreq, dack, ior#, and eot signals control transactions between the external dma controller and the net2272. dr eq and dack are minima lly needed to exchange data with the net2272, because the di rection (read) is established by the ep_cfg register endpoint direction bit. the operation mode is set by the dmareq register dma control dack bit. if the dma control dack bit is high, the net2272 needs dack and ior# for a dma read. if the bit is low, only dack is needed for a dma read. the local cpu programs the net2272 dmareq register to associate the dma dreq and dack signals with a net2272 endpoint (endpoint a or b). transfers occur only when the net2272 requests them, after the dmareq register dma request enable bit is set. when data is available in an endpoint buffer, and that endpoint is assigned to a dma channel, the dma request signal (dreq) is asserted. the external dm a controller then requests the local bus from the local bus master. after the external dma controller is granted the bus, the controller drives a valid memory address and asserts dack, ior# (optiona l), and external dma controller memw# output (to memory), thereby transf erring one byte from an endpoint buffer to local memory. in dma slow mode, the net2272 de-asserts dreq within t20 afte r the transaction starts. in dma fast mode, the net2272 de-asserts dreq when the transaction star ts. if data remains in the buffer, the net2272 re-asserts dreq. dma transfers co ntinue until the dma byte count reaches 0, or eot is asserted during the last dma transfer. the irqstat0 register dma done interrupt bit is set for the following conditions: eot is asserted during the last dma transfer local cpu writes a 0 to the ep_transfer x register after the dma transfer completes short packet is received and the endpoint buffers are empty when dma burst mode is selected, dreq is asserted when there is data in the buffer and the dma request enable bit is set. dreq remains asserted until one of the following conditions is met: buffer becomes empty dma request enable bit is cleared eot is asserted
august, 2005 dma read net2272 local bus to usb 2.0 peripheral controller data book 29 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 4.6.3.1 dma slow mode read timing in dma slow mode read timing, dreq is de-assert ed within t20 after the read transaction starts. dreq is re-asserted within t21 after the read tr ansaction ends. note: for 1.8, 2.5, and 3.3v vddio t timing values, refer to table 11-36 , table 11-46 , and table 11-56 , respectively. figure 4-8. dma slow mode read timing 4.6.3.2 dma fast mode read timing in dma fast mode read timing, dreq is de-asse rted when the read tran saction starts. dreq is re-asserted, either when the read transaction ends (i f the read enable width is greater than t21), or at t21 after the read transactio n starts (if the read enable width is less than t21). note: for 1.8, 2.5, and 3.3v vddio t timing values, refer to table 11-37 , table 11-47 , and table 11-57 , respectively. figure 4-9. dma fast mode read timing d0 d1 0ns 50ns 100ns 150ns dreq dack# ior# (optional) ld[15:0] eot# (optional) d0 d2 d1 0ns 25ns 50ns 75ns 100ns dreq dack# ior# (optional) ld[15:0] eot# (optional)
local bus interface plx technology, inc. 30 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 4.6.3.3 dma burst mode read timing in dma burst mode read timing, dreq remains asserted until the dma transfer completes. note: for 1.8, 2.5, and 3.3v vddio t timing values, refer to table 11-38 , table 11-48 , and table 11-58 , respectively. figure 4-10. dma burst mode read timing d0 d2 d1 0ns 25ns 50ns 75ns 100ns dreq dack# ior# (optional) ld[15:0] eot# (optional)
august, 2005 dma split bus mode net2272 local bus to usb 2.0 peripheral controller data book 31 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 4.6.4 dma split bus mode in dma split bus mode, the external dma controller is connected to ld[15:8] of the data bus, while the local cpu is connected to ld[7:0] of the data bus. the locctl register dma split bus mode bit enables dma split bus mode. dma split bus mode transactions are the same as normal dma transactions, except that dmard# and dmawr# are used instead of ior# and iow#, respectively. while dma transactions are proceeding using ld[15:8], the local cpu can simultaneously access configuration registers for any endpoint, and can access endpoint buffers not involved with the dma transfer. 4.6.5 terminating dma transfers the eot signal is used to halt dma transfers, and is typically provided by an external dma controller. assert eot while dack ? and optionally ior#, iow#, dmard#, or dmawr# ? are simultaneously active, to indicate that dma activity has stopped. although an eot signal indicates that a dma transfer has terminated, the usb transfer (in the case of an in transaction) is not complete until the last byte is transferred from the endpoint buffer to the usb. the eot input resets the dmareq register dma request enable bit. when eot is detected asserted, th e current endpoint buffer is automatically validated, causing data remaining in the current pack et to transmit to the host as a short packet. if there is no data in the buffer when the current buffer is validated, then a zero-len gth packet is returned in response to the next in token. the dma request enable bit is also automatically cleared when the ep_transfer x counter reaches 0 for in endpoints, or when the local cpu writes a 0 to the ep_transfer x counter. if the external dma controller does not provide an eot signal, the local cpu can terminate the dma transfer at any time by resetting the net2272 dma request enable bit. if the net2272 dma request enable bit is cleared during the mi ddle of a dma cycle (possible only when using dma split bus mode), the current cycle completes before dma reque sts are terminated. the e ndpoint buffer is not automatically validated when the dma request enable bit is cleared. in this case, the cpu must explicitly validate the packet by writing 0 to the ep_transfer x register.
local bus interface plx technology, inc. 32 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 4.6.6 dma performance at 3.3v vddio table 4-2 delineates dma performance specifications at 3.3v vddio. note: for t timing values, refer to table 11-53 through table 11-58 . note: * actual throughput in dma slow and fast modes is reduced if the dma controller dreq-to-dack delay is longer than 5 ns. table 4-2. dma performance specifications at 3.3v vddio transaction type mode specification value dma write slow* dreq to dack (depends on dma controller) 5 ns dack asserted to dreq de-asserted (t20) 50 ns dreq de-asserted to dreq asserted (t25) 25 ns 8-bit bus maximum performance 1/80 ns = 12.5 mb/s 16-bit bus maximum performance 2/80 ns = 25 mb/s fast* dreq to dack (depends on dma controller) 5 ns write width (t26) 5 ns dack de-asserted to dreq asserted (t21) 45 ns 8-bit bus maximum performance 1/55 ns = 18 mb/s 16-bit bus maximum performance 2/55 ns = 36 mb/s burst write width (t26) 5 ns write recovery (t30) 36 ns 8-bit bus maximum performance 1/41 ns = 24 mb/s 16-bit bus maximum performance 2/41 ns = 48 mb/s dma read slow* dreq to dack (depends on dma controller) 5 ns dack asserted to dreq de-asserted (t20) 50 ns dreq de-asserted to dreq asserted (t25) 25 ns 8-bit bus maximum performance 1/80 ns = 12.5 mb/s 16-bit bus maximum performance 2/80 ns = 25 mb/s fast* dreq to dack (depends on dma controller) 5 ns read width (t22) 16 ns dack de-asserted to dreq asserted (t21) 35 ns 8-bit bus maximum performance 1/56 ns = 17.8 mb/s 16-bit bus maximum performance 2/56 ns = 35.7 mb/s burst dma read cycle time (t17) 35 ns 8-bit bus maximum performance 1/35 ns = 28 mb/s 16-bit bus maximum performance 2/35 ns = 57 mb/s
net2272 local bus to usb 2.0 peripheral controller data book 33 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 chapter 5 usb functional description 5.1 usb interface the net2272 is a usb-function device, and as a result is a slave to the usb hos t. the bit- and packet- level protocols, as well as the net2272 electrical interface, conform to the usb r2.0 . the usb host initiates all usb data transfers to and from the net2272 usb port. the net2272 is configured for up to three physical and 30 virtual endpoints, in addition to endpoint 0. endpoints can be of type isochronous, bulk, or interrupt. the configuration registers are used to program endpoint characteristics. the net2272 op erates in full- (12 mbps) or high-speed (480 mbps) modes. 5.2 usb protocol the usb packet protocol consists of toke ns, packets, transactions, and transfers. 5.2.1 tokens tokens are a type of packet identifi er (pid), and follow the sync fiel d at the beginning of a token. the four classic token types are out, in, sof, and setup. in high-speed mode, the net2272 also recognizes the ping token. 5.2.2 packets there are four types of packets ? start-of-frame (sof), token, data, and handshake ? which are transmitted and received in the order listed in table 5-1 . each packet begins with a sync field and a packet identifier (pid). the other fiel ds vary, depending on the packet type. table 5-1 delineates the four usb protocol packet types. 5.2.3 transaction a transaction consists of a token packet, op tional data packet(s), and handshake packet. 5.2.4 transfer a transfer consists of one or more transactions. control transfers cons ist of a setup transaction, optional data transactions, and a status transaction. table 5-1. usb protocol packets packet type number of bits sync field packet identifier (pid) frame number address endpoint data cyclic redundancy checks (crc) total 1. start-of-frame (sof) 8 8 11 ? ? ? 5 32 2. token 8 8 ? 7 4 ? 5 32 3. data 8 8 ? ? ? n 16 32 + n 4. handshake 8 8 ? ? ? ? ? 16
usb functional description plx technology, inc. 34 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 5.3 automatic retries 5.3.1 out transactions if an error occurs during an out transaction, the net2272 reloads it s local bus buffer read pointer to the beginning of the failed packet. the host then transmits another out token and re-transmits the packet. after the net2272 successf ully receives the packet, the data packet received interrupt bit is set. the net2272 can handle any number of back-to-back retries; however, the host determines the number of packet retries. 5.3.2 in transactions if an error occurs during an in transaction, the net2272 reloads it s usb buffer read pointer to the beginning of the failed packet. the host then transmits another in token and the net2272 re-transmits the packet. after the host succe ssfully receives the packet, the data packet transmitted interrupt bit is set. 5.4 ping flow control when operating in high-speed mode, the net2272 supports ping protocol for bulk out and control endpoints. this protocol allo ws the net2272 to indicate to the host that it cannot accept an out packet. the host then transmits ping tokens to query the net2272. the net2272 returns an ack in response to the ping when it is able to accept a maximum-size packet. at this time, the host transmits an out token and data packet. the net2272 returns an ack handshake if the packet is accepted, and there is sufficient space to receive an additional packet. the net2272 returns a nyet handshake to the host if it can accept only the curren t packet. the host then starts transmitting ping tokens. 5.5 packet sizes an endpoint maximum packet size is determined by the corresponding ep_maxpkt x register. for in transactions, the net2272 returns a maximum-size packet to the host if the number of ?maximum packet? bytes exist in the buffer. if the bu ffer data is validated, a packet size less than the maximum is returned to the host in response to an in token. table 5-2 delineates the allowable maximum packet sizes. table 5-2. allowable maximum packet sizes endpoint type allowable maximum packet size (bytes) low-speed mode full-speed mode high-speed mode bulk n/a 8, 16, 32, 64 512 control 8 8, 16, 32, 64 64 interrupt 8 64 maximum 1,024 maximum isochronous n/a 1,023 maximum 1,024 maximum
august, 2005 usb endpoints net2272 local bus to usb 2.0 peripheral controller data book 35 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 5.6 usb endpoints the net2272 supports control, isochronous, bulk, and interrupt endpoints. all endpoints are uni-directional except for control endpoints. bi-dir ectional isochronous, bulk, and interrupt traffic requires two endpoints. 5.6.1 control endpoint (endpoint 0) the control endpoint, endpoint 0, is a reserved endpoint. the host uses this endpoint to configure and acquire information about the net 2272, its configurations, interfaces, and other endpoints. control endpoints are bi-directional, and data delivery is guaranteed. the host transmits 8-byte setup p ackets to endpoint 0, to which the net2272 interprets and responds. the net2272 consists of a set of registers dedicated to storing the setup packet, and uses the endpoint 0 packet buffer for control data. for control writes, data flows through the packet buffer from the usb-to-local bus. for control reads, data flows through the packet buffer from the local bus-to-usb. when endpoint 0 detects a setup packet, the net2272 sets status bits and interrupts the local cpu. the cpu reads the setup packet from net2272 registers, and responds based on the contents. the local cpu provides data to return to the hos t, including status and descriptors. refer to chapter 9, ?usb standard device requests ,? for a description of the data th at must be returned for each usb request. the host rejects descriptors that contain unexpected field values. 5.6.1.1 control write transfer a successful control write transfer to control e ndpoint 0 consists of the data delineated in table 5-3 . table 5-3. control write transfer transaction stage packet contents number of bytes source setup setup token setup pid, addr ess, endpoint, and crc5 3 host data data0 pid, 8 data bytes, and crc16 11 host status ack 1 net2272 data (zero, one, or more packets) out token out pid, addres s, endpoint, and crc5 3 host data (1/0) data pid, n data bytes, and crc16 n +3 host status ack 1 net2272 status in token in pid, address, endpoint, and crc5 3 host data data1 pid, zero-lengt h packet, and crc16 3 net2272 status ack 1 host
usb functional description plx technology, inc. 36 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 during the setup transaction, the net2272 stores th e data stage packet in its setup registers. the net2272 returns an ack handshake to the host after all eight bytes are received. a setup packet interrupt bit is set to notify the local cpu that a set up packet was received. the local cpu reads and interprets the 8-byte data packet. a setup transacti on cannot be stalled or naked; however, if the data is corrupt, the net2272 does not return an ack to the host. during the optional data transaction, zero, one, or more data packets are written into the endpoint 0 buffer. for each packet: 1. interrupt bits are set and can interrupt the local cpu. 2. local cpu reads the buffer. 3. net2272 returns an ack if no error occurred. for a successful status transaction, the net2272 re turns a zero-length data packet. a nak or stall handshake is returned if an error occurs. 5.6.1.2 control write transfer details for control write transfers, the host first transmits eight bytes of setup information. the setup bytes are stored into an 8-byte register ba nk that is accessed by the local cp u. after the eight bytes are stored into the setup registers, the setup packet interrupt bit is set. the local cpu then reads the 8-byte setup packet and prepares to respond to the optional data transaction. the number of bytes to transfer in the data transactions is specified in the setup p acket. when the setup packet is received, the control status stage handshake bit is automatically set, in anticipation of the control status transaction. while this bit is set, the control status transaction is acknowled ged with a nak, allowing the local cpu to prepare its handshake response (ack or stall). after the control status stage handshake bit is cleared and the out buffer is empty, an ack or stall hand shake is returned to the host. waiting for the out buffer to become empty prevents another contro l write from corrupting th e current packet data in the buffer. during a control write operation, optional data tran sactions can follow the setup transaction. the data out token interrupt bit is set at the beginning of each data transaction. the bytes corresponding to the data transaction are stored into the endpoint 0 buffer . if the buffer fills and the host transfers another byte, the net2272 returns a nak handshake to the host, signaling that the data cannot be accepted. if a packet is not successfully r eceived (nak or timeout status), the data packet received interrupt bit is not set, and the data is automatically flushed fr om the buffer. the host later re-transmits the same packet. this process is transparent to the local cpu. if the local cpu stalled this endpoint by setting the endpoint halt bit, the net2272 does not store data into the buffer, and responds with a stall acknowledge to the host. there is no status transaction in this case. the local cpu can poll the data packet received interrupt bit, or enable the bit as an interrupt, and then read the packet from the buff er. if the host tries to write more data than indicated in the setup packet, the local cpu sets the endpoint halt bit for endpoint 0. in this case, there is no status transaction from the host. after all optional data stage packets are received, th e host transmits an in toke n, signifying the status transaction. the control status interrupt bit is set after the status transaction in token is received. until the local cpu clears the control status stage handshake bit and the out buffer is empty, the net2272 responds with naks, indicating that the net2272 is processing the setup command. when the local cpu clears the control status stage handshake bit and firmware has emptied the out buffer data, the net2272 responds with a zero-length data packet (transfer ok) or stall (error encountered).
august, 2005 control endpoint (endpoint 0) net2272 local bus to usb 2.0 peripheral controller data book 37 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 5.6.1.3 control read transfer a successful control read transf er from control endpoint 0 consists of the data delineated in table 5-4 . the setup transaction is processed with the same method as control writ e transfers. (refer to section 5.6.1.2 .) during the optional data tran saction, zero, one, or more da ta packets are read from the endpoint 0 buffer. for each packet: 1. interrupt bits are set and can interrupt the local cpu. 2. local cpu writes data to the buffer. 3. if there is no data in the buffer, a nak or zero-length packet is returned to the host. 4. host returns an ack to the ne t2272 if no error occurred. for a successful status transactio n, the host transmits a zero-len gth data packet, and the net2272 responds with an ack. a nak or stal l is returned if an error occurred. 5.6.1.4 control read transfer details for control read transfers, the host first transmits eight bytes of setup information. the setup bytes are stored into an 8-byte register bank, accessed from the local cpu. af ter the eight bytes are stored into the setup registers, the setup packet interrupt bit is set. the local cpu then reads the 8-byte setup packet and prepares to respond to the optional data transaction. the number of bytes to transfer in the data transaction is specified in the setup p acket. when the setup p acket is received, the control status stage handshake bit is automatically set. while this bit is set, the control status transaction is acknowledged with a nak, allowing the local cpu to prepare its handshake response (ack or stall). after the control status stage handshake bit is cleared, an ack or stall handshake is returned to the host. during a control read operation, optional data transactions can follow the setup transaction. after the setup transaction, the local cpu can start writing the first byte of packet data into the endpoint 0 buffer, in anticipation of the data transaction. the data in token interrupt bit is set at the beginning of each data transaction. if there is data in the endpo int 0 buffer, the data is returned to the host. if endpoint 0 has no data to return, the endpoint returns a zero-length packet (signaling that no further data is available) or nak handshake (the data is not available). the net2272 responds to the data transaction in token, according to the data delineated in table 5-5 . table 5-4. control read transfer transaction stage packet contents number of bytes source setup setup token setup pid, addr ess, endpoint, and crc5 3 host data data0 pid, 8 data bytes, and crc16 11 host status ack 1 net2272 data (zero, one, or more packets) in token in pid, address, endpoint, and crc5 3 host data (1/0) data pid, n data bytes, and crc16 n +3 net2272 status ack 1 host status out token out pid, addre ss, endpoint, and crc5 3 host data data1 pid, zero-le ngth packet, and crc5 3 host status ack 1 net2272
usb functional description plx technology, inc. 38 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 note: ?x? is ?don?t care.? after each packet is tran smitted to the host, the data packet transmitted interrupt bit is set. if a packet is not successfully transmitted ( timeout status bit set), the data packet transmitted interrupt bit is not set, and this packet is transmitted to the host when another in to ken is received. the retry operation is transparen t to the local cpu. if the host tries to read more data than requested in the setup packet, the local cpu sets the stall bit for the endpoint. after all optional data stage packets are transmitted, the host transmits an out token, followed by a zero-length data packet, signifyi ng the status transaction. the control status interrupt bit is set after the status transaction out token is r eceived. until the lo cal cpu clears the control status stage handshake bit, the net2272 responds with naks, indicating that the net2272 is processing the command specified by the setup trans action. when the local cpu clears the control status stage handshake bit, the net2272 responds with an ack (tra nsfer ok) or stall (endpoint 0 is stalled). 5.6.2 isochronous endpoints isochronous endpoints are used for time-critical data transf ers. isochronous transfers do not support handshaking nor error-check ing protocol, and are guaranteed a certain amount of bandwidth during each frame. the net2272 sie ignores cyclic redundancy checks (crc) and bit-stuffing errors during isochronous transfers; however, the engine sets the ep_stat x register handshaking status bits the same as it sets for non-isochronous packets, enablin g the local cpu to detect the errors. isochronous endpoints are uni-directional, with the direction defined by the endpoint configuration registers. for isochronous endpoints, the packet buffer size must be equal to or greater than the maximum packet size. the maximum packet size for an isochronous endpoint ranges from 1 to 1,024 bytes. for an isochronous out endpoint, the local cpu or dma controller can read data from the endpoint buffer after an entire packet is received. if the en dpoint buffer is the same size as the maximum packet size, then the iso bandwidth must be set so the buffer is emptied befo re the next iso packet arrives. for an isochronous in endpoint, the local cpu or dma controller can write data to one endpoint buffer at the same time that data is being transmitted to the usb from the other endpoint buffer (double-buffered mode only). table 5-5. control read transfer details packet validated amount of data in buffer action 0 < maximum packet size nak to host x maximum packet size return data to host 1 empty zero-length packet to host 1 > 0 return data to host
august, 2005 isochronous endpoints net2272 local bus to usb 2.0 peripheral controller data book 39 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 5.6.2.1 isochronous out transactions isochronous out endpoints transfer data from a us b host to the net2272 local bus. an isochronous out transaction consists of the data delineated in table 5-6 . the usb host initiates an isochronous out transaction by transmitting an out token to an isochronous out endpoint. the data out token interrupt bit is set when the out token is recognized. the bytes corresponding to the data stage are stored into the endpoint buffer. isochronous transactions are not retrie d; therefore, if the buffer is full wh en the host transfers a packet (or the nak out packets bit is set), the packet is discarded. no handshake packets are returned to the host; however, the usb out ack transmitted and timeout status bits are set to indicate transaction status. if a crc error is detected, the packet is accepted, and the timeout status bit is set. after all data packets are received, the local cpu samples these status bits to determine whether the net2272 successfully received the packet. by definition, isochronous endpoints do not utili ze handshaking with the hos t. because there is no method to return a stalled handshake from an isochr onous endpoint to the host, data that is transmitted to a stalled isochronous endpoint is received normally . the maximum packet size must be less than or equal to the buffer size. the local cpu must wait for the data packet received interrupt bit to be set before reading the data from the buffer. if the endpoint is programmed for single-buffering, then the host is programmed to allow the local cpu sufficient time to unload the buffer before the next packet is transmitted. if the endpoint is programmed for double-buffering, then the local bus can unload one packet while the next packet is being received. table 5-6. isochronous out transactions stage packet contents number of bytes source out token out pid, addres s, endpoint, and crc5 3 host data data0 pid, n data bytes, and crc16 n +3 host
usb functional description plx technology, inc. 40 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 5.6.2.2 high-bandwidth isochronous out transactions the host transmits high-bandwid th out pid sequences for each microframe, depending on the endpoint descriptor additional transaction opportunities field, as delineated in table 5-7 . the net2272 accepts data (unless the endpoint bu ffer is full), and records the pid in the ep_hbw register high-bandwidth out transaction pid field. this allows firmware to track pids as they arrive and determine whether the data se quence is complete. (refer to table 5-8 .) table 5-7. high-bandwidth isochronous out transactions additional transaction opportunities pid sequence 0 data0 (normal iso) 1 mdata, data1 (one additional transaction) 2 mdata, mdata, data2 (two additional transactions) table 5-8. high-bandwidth isochronous out pid values high-bandwidth out transaction pid field pid received 00b data0 01b data1 10b data2 11b mdata
august, 2005 isochronous endpoints net2272 local bus to usb 2.0 peripheral controller data book 41 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 5.6.2.3 isochronous in transactions isochronous in endpoints transfer data from th e net2272 local bus to a usb host. an isochronous in transaction consists of the data delineated in table 5-9 . the usb host initiates an isochronous in transact ion by transmitting an in token to an isochronous in endpoint. the data in token interrupt bit is set when the in token is recognized. if there is data in the endpoint buffer, the data is returned to the host. if the endpoint has no data to return, a zero-length packet is returned to the host. the net2272 responds to the in toke n, according to the data delineated in table 5-10 . note: ?x? is ?don?t care.? after the packet is tran smitted to the host, the data packet transmitted interrupt bit is set. if an in token arrives and there is no valid packet in the endpoint buffer, the net2272 returns a zero-length packet. no handshake packets are returned to the host; however, the usb in ack transmitted and timeout status bits are set to indicate tr ansaction status. after all data p ackets are transmitted, the local cpu samples these status bits to determine whether the packets were successfully transmitted to the host. by definition, isochronous endpoints do not utili ze handshaking with the hos t. because there is no method to return a stalled handshake from an isochr onous endpoint to the host, data that is requested from a stalled isochronous endpo int is transmitted normally. table 5-9. isochronous in transactions stage packet contents number of bytes source in token in pid, addres s, endpoint, and crc5 3 host data data0 pid, n data bytes, and crc16 n +3 net2272 table 5-10. in token response packet validated amount of data in buffer action 0 < maximum packet size zero-length packet to host; usb in nak transmitted status bit set x maximum packet size return data to host 1 empty zero-length packet to host 1 > 0 return data to host
usb functional description plx technology, inc. 42 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 5.6.2.4 high-bandwidth isochronous in transactions a usb device that provides high-bandwidth iso in endpoints is required to transmit iso pid sequences for each microframe, accord ing to the endpo int descriptor additional transaction opportunities field in the corresponding ep_maxpkt x register, as delineated in table 5-11 . when the first microframe in toke n arrives, the net2272 copies the ep_maxpkt x register additional transaction opportunities field to determine the initial pid. on each succeeding microframe in token, the pid advances to the next token. 5.6.3 bulk endpoints bulk endpoints are used for guaranteed error-free delivery of large amounts of data between a host and device. bulk endpoints are uni-directional, with the direction defined by the endpoint configuration registers. 5.6.3.1 bulk out transactions bulk out endpoints transfer data from a us b host to the net2272 local bus. a bulk out transaction to a bulk out endpoint consists of the data delineated in table 5-12 . the usb host initiates a bulk out transaction by transmitting an out token to a bulk out endpoint. the data out token interrupt bit is set when the out token is recognized. the bytes corresponding to the data stage are stored into the endpoint buffer. if the buffer is full when the host transfers another packet, the packet is discarded and the usb out nak transmitted status bit is set. at packet completion, a nak handshake is returned to the host, indicating that the packet cannot be accepted. all usb data passes through endpoint buffers to the local bus. the cpu waits until the data packet received interrupt occurs before reading the buffer data. if a packet is not successfully received ( usb out nak transmitted or timeout status bits set), the data packet received interrupt bit is not set, and the data is automatically flushed from the buffer. the host later re-transmits the same packet. this process is transparent to the local cpu. if the local cpu stalled this endpoint by setting the endpoint halt bit, the net2272 does not store data into the buffer, and responds with a stall handshake to the host. table 5-11. high-bandwidth isochronous in transactions additional transaction opportunities pid sequence 0 data0 (normal iso) 1 data1, data0 (one additional transaction) 2 data2, data1, data0 (two additional transactions) table 5-12. bulk out transactions stage packet contents number of bytes source out token out pid, addre ss, endpoint, and crc5 3 host data (1/0) data pid, n data bytes, and crc16 n +3 host status ack, nak, or stall 1 net2272
august, 2005 bulk endpoints net2272 local bus to usb 2.0 peripheral controller data book 43 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 5.6.3.2 bulk in endpoints bulk in endpoints transfer data from the net2272 local bus to a usb host. a bulk in transaction from a bulk in endpoint consists of the data delineated in table 5-13 . the usb host initiates a bulk in transaction by transmitting an in token to a bulk in endpoint. the data in token interrupt bit is set when the in token is recognized. if there is validated data in the endpoint buffer, the data is returned to the host. if the endpoint has no data to return, a zero-length packet (signaling that no further data is available) or nak handshake (the data is not available yet) is returned. the net2272 responds to the in to ken, according to the data delineated in table 5-14 . note: ?x? is ?don?t care.? after the packet is transmitted to the host, the data packet transmitted interrupt bit is set. if a packet is not successfully transmitted ( timeout status bit set), the data packet transmitted interrupt bit is not set, and the same packet is transmitted to the ho st when another in token is received. the retry operation is transparent to the local cpu. if the local cpu stalled this endpoint by setting the endpoint halt bit, the net2272 responds to the in token with a stall handshake to the host. table 5-13. bulk in endpoints stage packet contents number of bytes source in token in pid, address, endpoint, and crc5 3 host data (1/0) data pid, n data bytes, and crc16, or nak or stall n +3 net2272 status ack 1 host table 5-14. bulk in endpoints packet validation packet validated amount of data in buffer action 0 < maximum packet size nak to host x maximum packet size return data to host 1 empty zero-length packet to host 1 > 0 return data to host
usb functional description plx technology, inc. 44 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 5.6.4 interrupt endpoints interrupt endpoints are used for transmitting or receiving small amounts of data to the host with a bounded service period. 5.6.4.1 interrupt out transactions interrupt out endpoints transfer data from a usb host to the net2272 local bus. an interrupt out transaction to an interrupt out endpoint consists of the data delineated in table 5-15 . the behavior of an interrupt out endpoint is essentially the same as a bulk out endpoint, except for the endpoint toggle bit. if the ep_rspclr/ep_rspset register interrupt mode bit is cleared, the interrupt out endpoint toggle bit is initialized to 0 (data0 pid), and behaves the same as a bulk out endpoint. if the interrupt mode bit is set, the interrupt out endpoint toggle bit changes after each data packet is received from the host, without re gard to the status stage. ping protocol is not allowed for interrupt out endpoints, as per the usb r2.0 . 5.6.4.2 interrupt in endpoints an interrupt in endpoint is polled at a rate specified in the endpoint descriptor. an interrupt transaction from an interrupt in endpoint consists of the data delineated in table 5-16 . the behavior of an interrupt in endpoint is the same as a bulk in endpoint, except for the toggle bit. if the ep_rspclr/ep_rspset register interrupt mode bit is cleared, the interrupt in endpoint toggle bit is initialized to 0 (data0 pid), and behaves the same as a bulk in endpoint. use interrupt endpoints to communicate rate feedback information for certain isochronous functions. to support this mode, the interrupt mode bit is set, and the interrupt in endpoint toggle bit changes after each data packet is transmitted to the host, without regard to the status stage. 5.6.4.3 high-bandwidt h interrupt endpoints from the usb device point of view, high-bandwidth in terrupt endpoints are the same as bulk endpoints, except that the maxpkt is a value from 1 to 1,024. normal interrupt endpoints in full-speed mode can set maxpkt from 1 to 64. table 5-15. interrupt out transactions stage packet contents number of bytes source out token out pid, address, endpoint, and crc5 3 host data (1/0) data pid, n data bytes, and crc16 n +3 host status ack, nak, or stall 1 net2272 table 5-16. interrupt in endpoints stage packet contents number of bytes source in token in pid, address, endpoint, and crc5 3 host data (1/0) data pid, n data bytes, and crc16 n +3 net2272 status ack 1 host
august, 2005 plx virtual endpoints net2272 local bus to usb 2.0 peripheral controller data book 45 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 5.7 plx virtual endpoints plx?s virtual endpoint hardware support allows a usb device to utilize the full potential of usb endpoints, by providing the capability to expose any number of endpoints to the usb host. firmware can track and assign the available physical endpoints to the dynamically required logical endpoints, with full flexibility. any number of endpoints required by a host driver (including usb class drivers) are supported. 5.7.1 overview the net2272 features plx virtual endpoint hardware support, which enables firmware to implement any number of usb device endpoints (up to a maximum of 15 per direction), excluding endpoint 0. (refer to the usb r2.0 , sections 8.3.2.2 and 9.6.6.) hardware support for endpoint virtualization consists of the virtual interrupt registers ? virtout0 , virtout1 , virtin0 , and virtin1 ? and the virtual endpoint interrupt status bit. in this section, ?logical endpoint? refers to the endpoint number from the host point of view (embedded in the out, in, and setup tokens), ?physical endpoint? refers to the net2272 hardware (endpoints 0, a, b, or c), and ?unassigned endpoint? refers to a logical endpoint number that is not currently assigned (by way of the ep_cfg register endpoint address field) to a physical endpoint. when the usbctl1 register virtual endpoint enable bit is low (default), the net2272 responds to a host request to an unassigned endpoint with a timeout. the host considers a timeout response as a fatal error. the host retries transactions with fatal errors; however, after 256 consecutive retries, the host shuts down the pipe (endpoint). when the virtual endpoint enable bit is high, the net2272 responds to all requests on unassigned endpoints with a nak. this causes the host to retry the request until an ack is returned. in addition to naking, the net2272 sets the bit in the virtual interrupt register that corresponds to the requesting logical endpoint number. for example , if the host requests an in token on endpoint 3 when none of the net2272 physical endpoints are assigned to address 3 with direction in, virtin0 register, bit 3, is set (and the net2272 naks the in request). when virtual endpoint register bits are set, the corresponding virtual endpoint interrupt status bit is also set. if this interrupt is en abled, firmware is notified that the host tried to access an unassigned endpoint. firmware can then re-assign one of the physical endpoints to the new logical endpoint, allowing the data transaction to proceed. virtual endpoint participation is completely flexible ? all physical endpoints (excluding endpoint 0) can participate in virtual endpoint re-assignment, or some physical endpoints are de dicated to specific high- usage logical endpoints. 5.7.2 endpoint virtualization virtualization relies on the firmware?s ability to capture, preserve, and restore the complete endpoint state as the firmware switches the available phys ical endpoint resources between a larger number of logical endpoints (similar to a cpu context switch). plx virtual endpoint hardware support makes all the endpoint state information available to the firmware. when re-assigning endpoints, firmware must ensure that usb traffic is not disturbed. specifically, an endpoint should not be reprogrammed or flushed while the endpoint is enabled. plx virtual endpoint hardware support includes logic to prevent an endpoint?s enable state from changing while a usb transaction to the endpoint is in pr ogress. therefore, firmware should first disable the endpoint, and then check that the enable succeeded (there can be a delay while a pending usb transaction completes).
usb functional description plx technology, inc. 46 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 to re-assign an in endpoint, firmware should proceed using one of th e following two methods. re-assign an in endpoint ? method a 1. stop loading data into the endpoint. 2. wait until there is no data waiting to be transmitted to the host (buffer states are available in the ep_buff_state register). because of the usb-in herent problem discussed in the usb r2.0 , section 8.5.3.3, waiting for the endpoint to empty can potentially lead to deadlock. 3. write 0 to the ep_cfg register endpoint enable bit. 4. verify that the endpoint enable bit is clear. 5. save the endpoint registers ? ep_cfg , ep_irqenb , ep_transfer x , ep_rspset , and ep_maxpkt x . 6. re-assign the endpoint. re-assign an in endpoint ? method b 1. stop loading data into the endpoint. 2. write 0 to the ep_cfg register endpoint enable bit. 3. verify that the endpoint enable bit is clear. 4. read the ep _ ava i l x register. 5. read out and store packets remaining loaded in the endpoint buffers. reading is accomplished by clearing the ep_cfg register endpoint direction bit, so the buffer data is available to ep_data and the count is available in ep _ ava i l x . zero-length packets should al so be detected, read out, and stored. zero-length packet s can be detected from the ep_buff_state register. 6. save the endpoint registers ? ep_cfg , ep_irqenb , ep_transfer x , ep_rspset , and ep_maxpkt x . 7. re-assign the endpoint. re-assign an out endpoint 1. write 0 to the ep_cfg register endpoint enable bit. 2. verify that the endpoint enable bit is clear. 3. if data is available in the endpoint buffer, read out the data. the host can transmit a packet after firmware clears the endpoint enable bit, before the endpoint is disabled. 4. save the endpoint registers ? ep_cfg , ep_irqenb , ep_transfer x , ep_rspset , and ep_maxpkt x . 5. re-assign the endpoint. re-assigning a physical endpoint consists of progr amming the direction, type, and logical endpoint number and setting the ep_cfg register endpoint enable bit (these operations can be executed in a single register write op eration), and loading the ep_irqenb , ep_transfer x , ep_rspset , and ep_maxpkt x registers. flush the endpoint before loading data or enabling the endpoint. restoring ep_rspset and ep_rspclr requires two register writes, one to ep_rspclr with the logical not of the saved ep_rspset value, and a second write to ep_rspset with the saved ep_rspset value. clearing the endpoint halt bit also clears the endpoint toggle bit, so the write to ep_rspclr should occur first, followed by the write to ep_rspset .
august, 2005 efficiency considerations net2272 local bus to usb 2.0 peripheral controller data book 47 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 when restoring an in endpoint with stored buffer data (refer to re-assign an in endpoint ? method b ), care should be taken to correctly restore ep_transfer x , using one of the following methods: load ep_transfer x with the stored ep_transfer x value, plus the count of stored data before the stored data is loaded load the stored data first (and packets validated by writing 0 to ep_transfer x ), followed by restoring ep_transfer x to the stored value 5.7.3 efficiency considerations depending on the number of virtual endpoints and the host-controller requirements, the firmware may need to prioritize virtual endpoint re-assignment. for example , a simple scheme of scheduling the lowest virtual endpoint request each time can starve higher logical endpoint addresses. round-robin priority is one method available to ensure that data travels on all endpoints. interrupt endpoints can require special care, because the polling interval between accesses can be excessive. it is not efficient to detect the endpoin t access on an interrupt endpoint (which was naked) ? switch to that endpoint, then detect and switch to a different endpoint before the next interrupt polling interval arrives. a possible solution is to ?lock down? the physical endpoint (prevent further endpoint switching) until a minimum number of packets pass through the endpoint. 5.7.4 deadlock considerations usually, the usb host controller retries naked bulk transactions in a round-robin priority; therefore, deadlocks do not normally occur. however, some host drivers can be susceptible to deadlocks. evaluate net2272 and host driver implementations, specifically for deadlock exposure. for example , step 2 of method a, re-assigning an in endpoint, requires firmware to wait until the physical endpoint is empty. (refer to re-assign an in endpoint ? method a .) deadlock occurs when the host is not requesting data on the (old) logical endpoint; instead, it is waiting for a transaction on the new logical endpoint (the logical endpoint firmware is trying to switch to the new logical endpoint; however, it is prevented from doing so b ecause the physical endpoint is not empty). this particular deadlock is broken by flushing the in endpoint if the net2272 is prepared to reload the packet(s), or if the data is discardable. alternativel y, deadlock is avoided by not loading data into the in logical endpoint until the host transmits an in token request, or by using method b, steps 2 through 4 , instead. (refer to re-assign an in endpoint ? method b .) another potential deadlock source is the usb-inherent problem discussed in the usb r2.0 , section 8.5.3.3. in this situation, the endpoint is unab le to flush the final packet of a transfer because the endpoint does not know that the ho st correctly received the packet, a nd the host cannot transmit another in token request on the same endpoint for an indeterminate length of time. 5.7.5 buffer control the net2272 buffers are read and wr itten from the local bus. this feat ure is used for chip diagnostics (power-on tests) and during virtual endpoint context switching. when the ep_cfg register endpoint direction bit (bit 4) of an endpoint is set, the endpoint is an in endpoint and ep_data is a write-only fifo-style register. after data is loaded into the endpoint, the packet is validated by writing 0 to ep_transfer x (as a convenience, if the upper two bytes of ep_transfer x are 0, writing 0 to ep_transfer0 validates the packet with a single register write). after a packet is validated (or both packets have b een validated if the endpoint is configured to be double-buffered), the endpoint direction bit is switched to out (by clearing the ep_cfg register endpoint direction bit) and the buffer da ta can be read out. the ep _ ava i l x registers indicate the number of bytes available in the buffer.
usb functional description plx technology, inc. 48 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 zero-length packets behave the same as out zero -length packets tr ansmitted by the host, and are similarly flushed by a dummy read from the ep_data register. the presence of a zero-length packet is indicated by the ep_stat1 register local out zlp bit (bit 6) or by the ep_buff_states buffer states. data is available for reading from the out ep_data register only after the packet is validated and while the endpoint is configured for in. written, unvalidated data is lost when the direction is switched to out. the endpoint should be disabled before switching directions, and the disable operation checked by reading bit 7 of the ep_cfg register, endpoint enable . this ensures that the usb host does not read the in packet before local firmware reads out the packet. ep_data buffers can be read or written while the endpoint is disabled. 5.8 packet buffers the net2272 contains one 3-kb memory bank, allocated to endpoint packet buffers. endpoint a and b buffer configuration is selected by the locctl configuration register buffer configuration field. available configurations for endpoints a and b are as follows: 512 bytes, double-buffered (total of 1 kb) 1,024 bytes, single-buffered 1,024 bytes, double-buffered the combined size of all endpoint a and b buffers cannot exceed 2 kb. endpoint c has a 1-kb buffer, configured as two 512-byte buffers. endpoint 0 has a 128-byte buffer, configured as two 64-byte buffers. data is stored into the buffers in 32-bit dwords, allowing each entry to contain between 1 and 4 bytes. if a write to a full buffer is detected, the data is ignored. if a read from an empty buffer is detected, undefined data is presented on the data bus. 5.8.1 out endpoint buffers when receiving data, the net2272 naks the host (indicating that the net2272 cannot accept the data) when one of the following conditions is met: buffer is full nak out packets mode and nak out packets bits are set if the packets received are of maxi mum size, then additional packets are received, independent of the nak out packets mode bit state. this bit causes additional out packets to be naked if the last packet received was a short packet. if the nak out packets mode bit is true (blocking mode), usb out transfers can overlap with the local cpu, un loading the data in the following sequence: 1. local cpu responds to the data packet received interrupt bit and reads the ep _ ava i l x register to determine the number of bytes in the current packet. 2. local cpu clears the data packet received interrupt and nak out packets bits, allowing the next packet to be received. 3. local cpu can now unload data from the bu ffer during the next usb out transaction. if the nak out packets mode bit is false (non-blocking mode), the net2272 accepts packets as long as there is space for the complete packet in the next available buffer. there are no indications of packet boundaries when buffers in a double-buffered configuration consist of multiple packets.
august, 2005 in endpoint buffers net2272 local bus to usb 2.0 peripheral controller data book 49 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 5.8.2 in endpoint buffers in packet data is written by the local cpu or dma controller into one of the in endpoint buffers. after the buffer data is validated, the data is returned to the usb host in response to an in token. the net2272 does not transmit more than the specified number of ep_maxpkt x bytes (quantity indicated by the register value) pe r packet. after a packet is written into a double-buffered buffer and validated, the local cpu can continue loading data for the next packet. the net2272 automatically divides the data flow into individual packets, with a maximum packet size determined by the associated ep_maxpkt x register. this allows usb transactions to overlap with loading of data from the local bus. if the buffer data is not validated, the net2272 responds to an in token with a nak handshake. there are several methods for validating in buffer data: for large amounts of data, the local bus controller can write data to the buffer as long as buffer space is available. when there are at least the specified number of ep_maxpkt x bytes in the buffer, the net2272 responds to an in token with a data packet. if the entire data transfer is a multiple of the speci fied number of ep_maxpkt x bytes, no further action is required to validate the buffer data. if a zero-length packet must be transmitted to the host, the local cpu can write 0 to the ep_transfer x register without writing additional data to the buffer. for moderate amounts of data (between ep_maxpkt x and 16 mb), the ep_transfer x counter is used. this counter is initialized to the total transfer byte count before data is written to the buffer. also, the counter decrements as da ta is written to the buffer. when the counter reaches 0, data remaining in the buffer is vali dated. if 16-bit transfer s are being utilized on the local bus, excess bytes in the last word are automati cally ignored. if the last packet of a transfer contains ep_maxpkt x bytes, the net2272 responds to the next in token with a zero-length packet. for small amounts of data (character-oriented applications), the data is first written to the buffer. a 0 is then written to the ep_transfer x register, thereby causing the data to be validated. for a dma write terminated with an eot, the buffer data is validated if the dmareq register dma buffer valid bit is set, which causes a short- or zero-length packet to transmit in response to the next in token. note: up to two short packets (fewer than the specified number of ep_maxpktx bytes) can be stored in a double-buffered packet buffer. 5.8.2.1 16-bit post-validation post-validation is a technique in which data is written to the buffer before the data is validated. to post-validate an odd-length packet (size 2 n +1) when operating in 16-bit mode, use the following sequence: 1. write 2 n bytes, using n 16-bit transactions to the endpoint buffer, by way of ep_data . 2. change to an 8-bit bus by clearing the locctl register data width bit. 3. write the last byte to the endpoint buffer by way of ep_data . 4. post-validate the buff er by writing 0 to ep_transfer0 . 5. return to a 16-bit bus by setting the locctl register data width bit.
usb functional description plx technology, inc. 50 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 5.9 usb test modes use the xcvrdiag register force full speed and force high speed bits to force the net2272 into full- and high-speed modes, respectively. these bits must not be used in normal operation , as they are for testing purposes only. in normal operation, the net2272 automatically performs usb r2.0 -chirp protocol negotiation with the host to determine the correct operating speed. usb r2.0 test mode support is provided by way of the usbtest register usb test mode select field. this field selects the appropriate us b test mode settings. (refer to the usb r2.0 , section 9.4.9, for further details.) normally, the host transmits a set_feature request with the test selector in the upper byte of windex . to select the correct test mode, copy the test selector into the usbtest register usb test mode select field. usb test mode settings are functional only when the net2272 is in high-speed mode. also, if the net2272 is operating in high-speed mode, and the usb test mode select field is set to non-zero, the net2272 is prevented from switching out of high-speed mode. normal usb suspend and reset, as well as the force full speed and force high speed bits, are ignored for test purposes. the net2272 can be forced into high-speed mode (using the force high speed bit), regardless of whether the net2272 is connected to a host controller. after choosing high-speed mode, usb test modes can be selected. most usb test modes require no further support from the net2272 firmware. however, the test_packet (100b) test selector requires the net2272 to return a specific packet. firmware performs the following se quence to activate the test mode: 1. sets the usb test mode select field to 100b. 2. flushes endpoint 0. 3. loads the following 53 (35h) hex byte packets into endpoint 0: 00 00 00 00 00 00 00 00 - 00 aa aa aa aa aa aa aa aa ee ee ee ee ee ee - ee ee fe ff ff ff ff ff ff ff ff ff ff ff 7f bf df - ef f7 fb fd fc 7e bf df ef f7 fb fd 7e validate the packet with a normal validation method, such as pre-validating by writing 35h into ep_transfer0 before loading the bytes, or writing 0 to ep_transfer0 after loading the bytes.
net2272 local bus to usb 2.0 peripheral controller data book 51 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 chapter 6 interrupt and status register operation 6.1 overview the purpose of this chapter is to describe, in genera l terms, how interrupt and status registers operate. for in-depth details of all interrupt bits, refer to chapter 8, ?configuration registers .? 6.2 interrupt status registers (irqstat0 and irqstat1) bits [3:0] of the irqstat0 register, endpoint interrupt , indicate whether an interrupt is pending on endpoint c, b, a, or 0, respectively. these bits ca nnot be written, and can cause a local interrupt if the corresponding irqenb0 register interrupt enable bits are set. bit 7 is automatically set when a start- of-frame (sof) token is received, and cleared by writing 1. bit 7 can cause a local interrupt if the corresponding irqenb0 register interrupt enable bit is set. interrupt bits can be set without the corresponding interrupt enable bit being set. this allows the local cpu to operate in a polled and/or interrupt-driven environment. irqstat0 register bits [6:4] and irqstat1 register bits [7:4 and 2:1] are set when a particular event occurs in the net2272, and cleared by writing 1 to the corresponding bit. these bits can cause a local interrupt if the corresponding irqenb0 and irqenb1 register interrupt enable bits are set. irqstat1 register bit 3 is set when the host transmits a suspend request; however, the bit is not typically enabled to generate an interrupt. writing 1 clears this bit and causes the net2272 to enter the low-power suspend state. 6.3 endpoint response registers (ep_rspclr and ep_rspset) each endpoint maintains of a pair of endpoint response registers. these registers determine how the net2272 responds to various situations during usb transactions. writing 1 to any ep_rspclr register bit clears the corresponding bit. writing 1 to any ep_rspset register bit sets the corresponding bit. reading e ither of these registers retu rns their current bit states. 6.4 endpoint status register (ep_stat0 and ep_stat1) each endpoint maintains a pair of endpoint status registers. the ep_stat x register bits are set when a particular endpoint event occurs, an d cleared by writing 1 to the corr esponding bit. a local interrupt can be generated if the corresponding ep_irqenb register interrupt enable bits are set. reading the ep_stat x registers returns their current bit states.
interrupt and status register operation plx technology, inc. 52 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91
net2272 local bus to usb 2.0 peripheral controller data book 53 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 chapter 7 power management 7.1 overview the net2272 supports the usb power management requirements detailed in the usb r2.0 . 7.2 usb low-power suspend state when there is a 3 ms peri od of usb inactivity, the usb r2.0 requires bus-powered devices to enter into the low-power suspend state. during this state, bus- powered devices can draw no more current than the maximum value listed in table 7-1 . to facilitate this, the net2272 provides the irqstat1 register suspend request change interrupt and suspend request interrupt bits. additionally, the net2272 allows local bus hardware to initiate a device-remote wakeup to the usb. 7.2.1 suspend sequence the typical suspend sequence is as follows: 1. during device configuration, the local cpu enables the irqstat1 register suspend request change interrupt bit to generate a local interrupt. 2. when the usb is idle for 3 ms, the net2272 sets the suspend request change interrupt bit, generating an interrupt to the local cpu. this interrupt also occurs when the net2272 is not connected to a host and the usb data lines are pull ed to the idle state (dp high, dm low), or the vbus input is low. 3. the local cpu accepts this interrupt by clearing the suspend request change interrupt bit, and performs the required tasks, en suring that no more than 500 ma of current is drawn from the usb power bus. 4. the local cpu writes a 1 to the irqstat1 register suspend request interrupt bit to initiate the transition to the low-power suspend state. 5. lclko continues to operate for 500 s before th e net2272 enters the low-power suspend state. this allows time for a local cpu using lclko to power down. 6. a device-remote wakeup event is not recognized during the 500 s suspend delay period. in the low-power suspend state, the net2272 oscillator shuts down, and most output pins/balls are three-stated to conserve power. (refer to chapter 2, ?pin/ball description .?) do not allow the net2272 input pins/balls to float during this state. the net2272 exits the low-power suspend state by detecting a host-initiated or device-remote wakeup. if the net2272 is self-powered, it can ignore the us b suspend request and never write 1 to the suspend request interrupt bit. note: configuration registers cannot be accessed when the net2272 is in the low-power suspend state. table 7-1. bus-powered device maximum currents in low-power suspend state device maximum current low powered 500 a high powered 2.5 ma
power management plx technology, inc. 54 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 7.2.2 host-initiated wakeup the host can wake up the net2272 by driving a non-idle state on the usb. the net2272 detects the host?s wakeup request, and restarts its internal os cillator. the host-initiated wakeup is recognized only when the vbus input pin/ball is high, and the usbctl0 register usb detect enable and usb root-port wakeup enable bits are set. 7.2.3 device-remote wakeup the net2272 hardware signals a usb device-remote wakeup by driving cs# input pin/ball low. if the usbctl0 register i/o wakeup enable bit is set, the net2272 restarts its local oscillator. two milliseconds after cs# is asserted , the local cpu must write to the usbctl1 register generate resume bit. this transmits a 10-ms wakeup signal to the usb host. 7.2.4 resume interrupt when the net2272 starts a device-remote or host-initiated wakeup, the net2272 can also be programmed to generate a resume interrupt. the irqstat1 register resume interrupt bit is set when a resume is detected, and enabled to generate an interrupt with the resume interrupt enable bit. 7.3 net2272 power configuration the usb r2.0 defines both bus-powered and self-powered devices. a bus-powered device is a peripheral that derives its power from the upstream usb connector. a self-powered device derives its power from an external power supply. the most significant consideration when deciding whether to build a bus- or self-powered device is power consumption. the usb r2.0 dictates the following requirem ents for maximum current draw: device not host-configured can draw only 100 ma from the usb connector power pins. device can draw no more than 500 ma from the usb connector power pins. in the low-power suspend state, however, the device can draw no more than 500 a (or 2.5 ma for a high-power device) from the usb connector power pins. warning: if these power considerations can be met without using an external power supply, it is recommended that the net2272 be bus-powere d; otherwise, implement a self-powered design. harm, such as ground shorting, ca n occur to the net2272 if the proper power design is not used. 7.3.1 self-powered device generally, a device with higher power requirements is self-powered. in a self-powered device, the net2272 vddc and vddio pins/balls are powered by the local power supply. this allows the local bus to continue accessing the net2272, although the net2272 cannot be connected to the usb. the usb connector power pin is directly connected to the net2272 vbus pin/ball, and is used only to detect whether the device is connected to the usb host. while the device is connected to the usb host, the net2272 automatically requests the low-power suspend state when appropriate. do not power-down the net2272 when its local bus is connected to a powered-up device. there are esd protection circu its in the net2272 that short vddc and vddio pins/balls to ground. if the vddc and vddio pins/balls are not powered, they sink excessive current from the board.
august, 2005 net2272 low-power modes net2272 local bus to usb 2.0 peripheral controller data book 55 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 7.4 net2272 low-power modes 7.4.1 usb suspend (unplugged from usb) the net2272 can draw a small amount of power when disconnected from the usb. disconnecting from the usb is accomplished in two ways: unplug the usb cable clear the usbctl0 register usb detect enable bit in power-sensitive applications, the local cpu can force the net2272 to enter the low-power suspend state when disconnected from the usb by writing 1 to the suspend request interrupt bit. the net2272 automatically wakes up when the pe ripheral device is re-connected to the usb (cable is plugged in and usb detect enable bit is set). caution: do not force the low-power suspend state, unless the peripheral device is disconnected from the usb host. when the net2272 is conn ected to the usb, it is a violation of the usb r2.0 to enter this state unless the upstream port is idle for at least 3 ms. usb suspend is the preferred method of suspe nding the net2272, because a usb re-connection automatically causes the net2272 to wakeup and set the resume interrupt bit. 7.4.2 power-on standby the local cpu can prevent the net2272 from starting its oscillator upon power-up by driving a low into the cs# pin/ball while reset# is asserted (l ow). in the low-power su spend state, the net2272 requires only a minor quiescent standby current. when the peripheral device requires starting of the oscillator, the lo cal cpu releases the cs# pin/ball and continues to assert reset# for a minimum of 2 ms. while the oscillator is stopped, the net2272 cannot respond to usb requests; ther efore, the oscillator must be a llowed to start when the peripheral device detects a usb connection event. the local cp u is responsible for detecting the connection, and ending the standby condition. power-on standby is appropriate when the device?s power budget does not allow the net2272 to be active a sufficient amount of time to shut itself down by setting the suspend request interrupt bit.
power management plx technology, inc. 56 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91
net2272 local bus to usb 2.0 peripheral controller data book 57 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 chapter 8 configuration registers 8.1 register description the net2272 occupies a 32-byte address space that can be accessed by a local cpu. registers can be directly or indirectly accessed throug h a pointer register. directly acce ssing the register s provides higher performance, while accessing the regist ers through the pointer register requires fewer physical address pins/balls. the most commonly used registers are located at the lowest addresses, thereby providing the highest performance when using fewer than five address bits. each configuration register is organized as an 8-bi t register, while the endpoint packet buffers can be accessed as an 8- or 16-b it port, depending on the locctl register data width bit value. after the net2272 is powered-up or reset, the regist ers are set to their default values. writes to unused registers are ignored, and reads from unused registers return a value of 0. always write register reserved bits with a 0, to maintain compatibility with future revisions. note: configuration registers cannot be accessed when the net2272 is in the low-power suspend state. this chapter describes the three register groups: main control usb control endpoint 8.2 register address mapping table 8-1. main control register address mapping address register name register description page 00h regaddrptr indirect regi ster address pointer 62 01h regdata indirect register data 62 02h irqstat0 interrupt status (low byte) 63 03h irqstat1 interrupt status (high byte) 64 04h pagesel endpoint page select 64 1ch dmareq dma request control 65 1dh scratch scratchpad 65 20h irqenb0 interrupt enable (low byte) 66 21h irqenb1 interrupt enable (high byte) 67 22h locctl local bus control 68 23h chiprev_legacy legacy silicon revision 68 24h locctl1 local bus control 1 69 25h chiprev_2272 net2272 silicon revision 69
configuration registers plx technology, inc. 58 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 table 8-2. usb control register address mapping address register name register description page 18h usbctl0 usb control (low byte) 70 19h usbctl1 usb control (high byte) 70 1ah frame0 frame counter (low byte) 71 1bh frame1 frame counter (high byte) 71 30h ouraddr our current usb address 71 31h usbdiag usb diagnostic 71 32h usbtest usb test modes 72 33h xcvrdiag transceiver diagnostic 72 34h virtout0 virtual out interrupt 0 73 35h virtout1 virtual out interrupt 1 73 36h virtin0 virtual in interrupt 0 73 37h virtin1 virtual in interrupt 1 73 40h setup0 setup byte 0 74 41h setup1 setup byte 1 74 42h setup2 setup byte 2 74 43h setup3 setup byte 3 74 44h setup4 setup byte 4 75 45h setup5 setup byte 5 75 46h setup6 setup byte 6 75 47h setup7 setup byte 7 75
august, 2005 register address mapping net2272 local bus to usb 2.0 peripheral controller data book 59 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 note: there is a set of endpoint regi sters for each endpoint. the pagesel register page select field selects which register set is active when the addresses in table 11-3 are accessed. table 8-3. endpoint register address mapping address register name register description page 05h ep_data endpoint data 76 06h ep_stat0 endpoint status (low byte) 77 07h ep_stat1 endpoint status (high byte) 78 08h ep_transfer0 in endpoint transfer count (byte 0) 78 09h ep_transfer1 in endpoint transfer count (byte 1) 79 0ah ep_transfer2 in endpoint transfer count (byte 2) 79 0bh ep_irqenb endpoint interrupt enable 79 0ch ep_avail0 endpoint available count (low byte) 80 0dh ep_avail1 endpoint ava ilable count (high byte) 80 0eh ep_rspclr endpoint response clear 81 0fh ep_rspset endpoi nt response set 82 28h ep_maxpkt0 endpoint maximum packet size (low byte) 82 29h ep_maxpkt1 endpoint maximum packet size (high byte) 82 2ah ep_cfg endpoint configuration 83 2bh ep_hbw endpoint high bandwidth 83 2ch ep_buff_states endpoint buffer states 84
configuration registers plx technology, inc. 60 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 8.3 numeric register listing table 8-4 lists the quantity of address bits required to directly access a regi ster. if only four address bits are supplied to the net2272, then registers that require five address bits must be indirectly addressed, using the regaddrptr and regdata registers. addresses marked with (p) are pa ged registers, selected by the pagesel register page select field. table 8-4. numeric register listing address required address bit quantity ld[15:8] ld[7:0] register description 00h 1 regaddrptr register address pointer fo r indirect regist er addressing. 01h regdata1 regdata register data port for indirect regi ster addressing. 02h 2 irqstat0 interrupt status (low byte). 03h irqstat1 interrupt status (high byte). 04h 3 pagesel page select. se lect current endpoint. 05h (p) ep_data1 ep_data endpoint data. 06h (p) ep_stat0 endpoint main status. 07h (p) ep_stat1 08h (p) 4 ep_transfer0 for in endpoint, number of bytes to transmit to the host. 09h (p) ep_transfer1 0ah (p) ep_transfer2 0bh (p) ep_irqenb endpoint interrupt enable. 0ch (p) ep_avail0 for in endpoints, numbe r of available spaces in buffer. 0dh (p) ep_avail1 for out endpoints, number of bytes in buffer. 0eh (p) ep_rspclr endpoint response clear. 0fh (p) ep_rspset en dpoint response set. 10h - 17h 5 reserved 18h usbctl0 usb control. 19h usbctl1 1ah frame0 frame counter. 1bh frame1 1ch dmareq dma request control. 1dh scratch general-purpose scratchpad. 1eh - 1fh reserved
august, 2005 numeric register listing net2272 local bus to usb 2.0 peripheral controller data book 61 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 20h indirect only irqenb0 interrupt enable. 21h irqenb1 22h locctl local bus control. 23h chiprev_legacy legacy chip revision number. 24h locctl1 local bus control 1. 25h chiprev_2272 net2272 chip revision number. 26h - 27h reserved 28h (p) ep_maxpkt0 endpoint maximum packet size. 29h (p) ep_maxpkt1 2ah (p) ep_cfg endpoint configuration. 2bh (p) ep_hbw endpoint high bandwidth. 2ch (p) ep_buff_states endpoint buffer states. 2dh - 2fh reserved 30h ouraddr our usb address. 31h usbdiag usb r2.0 diagnostic. 32h usbtest usb r2.0 test control. 33h xcvrdiag transceiver diagnostic. 34h virtout0 virtual out interrupt 0. 35h virtout1 virtual out interrupt 1. 36h virtin0 virtual in interrupt 0. 37h virtin1 virtual in interrupt 1. 38h - 3fh reserved 40h setup0 setup byte 0. 41h setup1 setup byte 1. 42h setup2 setup byte 2. 43h setup3 setup byte 3. 44h setup4 setup byte 4. 45h setup5 setup byte 5. 46h setup6 setup byte 6. 47h setup7 setup byte 7. table 8-4. numeric register listing (cont.) address required address bit quantity ld[15:8] ld[7:0] register description
configuration registers plx technology, inc. 62 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 8.4 main control registers register 11-1. (address 00h; regaddrpt r) indirect register address pointer bits description read write default 6:0 register address register address pointer used fo r indirect regi ster addressing. ye s ye s 0 h 7 reserved ye s n o 0 register 11-2. (address 01h; re gdata) indirect register data bits description read write default 15:0 register data register data port for indirect register addressing. for 8-bit bus widths, data is transferred on bits [7:0 ]. for 16-bit buffer access es, data is transferred on bits [15:0]. yes yes 0 h
august, 2005 main control registers net2272 local bus to usb 2.0 peripheral controller data book 63 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 register 11-3. (address 02h; irqsta t0) interrupt status (low byte) bits description read write default 0 endpoint 0 interrupt conveys interrupt status for endpoint 0. when set, the endpoint 0 interrupt status register is read to determine the interrupt cause. endpoint 0 interrupt is set independently of the interrupt enable bit. yes n o 0 1 endpoint a interrupt conveys interrupt status for endpoint a. when set, the endpoint a interrupt status register is read to determine the interrupt cause. endpoint a interrupt is set independently of the interrupt enable bit. yes n o 0 2 endpoint b interrupt conveys interrupt status for endpoint b. when set, the endpoint b interrupt status register is read to determine the interrupt cause. endpoint b interrupt is set independently of the interrupt enable bit. yes n o 0 3 endpoint c interrupt conveys interrupt status for endpoint c. when set, the endpoint c interrupt status register is read to determine the interrupt cause. endpoint c interrupt is set independently of the interrupt enable bit. yes n o 0 4 virtual endpoint interrupt set when a virtual endpoint interrupt is set. yes n o 0 5 setup packet interrupt set when a setup packet is received fr om the host. writing 1 clears this bit. yes ye s/ c lr 0 6 dma done interrupt for in endpoints, indicates that eot was asserted, the ep_transfer x counter reached 0 during a dma transfer, or the corresponding ep_transfer x counter was loaded with a 0. for out endpoints, indicates one of the following: eot is asserted during the last dma transfer local cpu writes a 0 to the ep_transfer x register after the dma transfer completes short packet is received and the endpoint buffers are empty writing 1 clears this bit. dma done interrupt is set independently of the corresponding interrupt enable bit. yes ye s/ c lr 0 7 sof interrupt indicates when the net2272 receives a start-of-frame (sof) packet. writing 1 clears this bit. set ever y 1 ms for full-speed connections, and every 125 s for high-speed connections. yes ye s/ c lr 0
configuration registers plx technology, inc. 64 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 register 11-4. (address 03h; irqsta t1) interrupt status (high byte) bits description read write default 0 reserved yes n o 0 1 control status interrupt set when an in or out token indi cates a control status transaction was received. writing 1 clears this bit. yes ye s/ c lr 0 2 vbus interrupt when set, indicates a change occurred on the vbus input pin/ball. read the usbctl1 register for the vbus input pi n/ball?s current state. writing 1 clears this bit. yes ye s/ c lr 0 3 suspend request interrupt set when the net2272 detects a usb suspend request from the host. the suspend request state cannot be set nor cl eared by writing th is bit. instead, writing 1 to this bit places the net2272 into the low-power suspend state. (refer to section 7.2.1 .) yes yes/suspend 0 4 suspend request change interrupt set when there is a change in the suspend request interrupt state (bit 3 of this register). writing 1 clears this bit. yes ye s/ c lr 0 5 resume interrupt when set, indicates that a device resu me occurred. writing 1 clears this bit. yes ye s/ c lr 0 6 root-port reset interrupt indicates a change in the root-port reset detector state. writing 1 clears this bit. yes ye s/ c lr 0 7 reset status when set, indicates that reset# is asserted, or a usb root-port reset is currently active. yes n o 0 register 11-5. (address 04h; pa gesel) endpoint page select bits description read write default 1:0 page select the net2272 uses a paged architecture for accessing the endpoint registers. selects which endpoint register set can be accessed. values: 00b = endpoint 0 01b = endpoint a 10b = endpoint b 11b = endpoint c yes yes 00b 7:2 reserved yes n o 0 h
august, 2005 main control registers net2272 local bus to usb 2.0 peripheral controller data book 65 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 register 11-6. (address 1ch; dmareq) dma request control bits description read write default 0 dma endpoint select determines which endpoint is acce ssed during a dma channel transfer. va l u e s : 0 = endpoint a 1 = endpoint b ye s ye s 0 1 dreq polarity when clear, dreq output pin/ball is active low. when set, dreq output pin/ball is active high. ye s ye s 1 2 dack polarity when clear, dack input pin/ball is ac tive low. when set, dack input pin/ ball is active high. ye s ye s 0 3 eot polarity when clear, eot input pin/ba ll is active low. when se t, eot input pin/ball is active high. ye s ye s 0 4 dma control dack when clear, only dack is used to perform dma read or write transactions. when set, the ior# and iow# (or dmard# and dmawr# for dma split bus mode) control signa ls are used with dack to perform dma read or write transactions. ye s ye s 0 5 dma request enable writing 1 enables the net2272 to re quest dma cycles from a local bus dma controller. if eot input is asserted, the ep_transfer x counter reaches 0, or a short out packet is received an d the endpoint buffer is empty, dma request enable is automatically reset. a local bus cpu can also explicitly reset this bit to terminate a dma transfer. if the cpu writes a 0 to the ep_transfer0 register of the endpoint selected by page select , this bit is cleared. dma request enable can be read to de termine whether a dma transfer remains in progress. ye s ye s 0 6 dma request reflects dreq output pin/ ball state, and allows a local bus cpu to monitor dma transfers. ye s n o 0 7 dma buffer valid when clear, the buffer is not automatically validated at the end of a dma transfer. when set, the buffer is automatically validated at the end of a dma transfer if eot is assert ed. applies only to in endpoints. ye s ye s 0 register 11-7. (address 1dh; scratch) scratchpad bits description read write default 7:0 scratch general-purpose scratchpad register. yes yes 5ah
configuration registers plx technology, inc. 66 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 register 11-8. (address 20h; irqe nb0) interrupt enab le (low byte) bits description read write default 0 endpoint 0 interrupt enable when set, enables a local interrupt to be set when an interrupt is active on endpoint 0. yes yes 0 1 endpoint a interrupt enable when set, enables a local interrupt to be set when an interrupt is active on endpoint a. yes yes 0 2 endpoint b interrupt enable when set, enables a local interrupt to be set when an interrupt is active on endpoint b. yes yes 0 3 endpoint c interrupt enable when set, enables a local interrupt to be set when an interrupt is active on endpoint c. yes yes 0 4 virtual endpoint interrupt enable when set, enables a local interrupt to be generated when an in or out token to a virtual endpoint is detected. yes yes 0 5 setup packet interrupt enable when set, enables a local interrupt to be generated when a setup packet is received from the host. yes yes 0 6 dma done interrupt enable when set, enables a local interr upt to be generated when the irqstat0 register dma done interrupt status bit is set. yes yes 0 7 sof interrupt enable when set, enables a local interrupt to be generated when the net2272 receives a start-of-frame (sof) packet. yes yes 0
august, 2005 main control registers net2272 local bus to usb 2.0 peripheral controller data book 67 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 register 11-9. (address 21h; irqe nb1) interrupt enab le (high byte) bits description read write default 0 reserved yes n o 0 1 control status interrupt enable when set, enables a local interrupt to be generated when an in or out token indicates a control stat us transaction was received. yes yes 0 2 vbus interrupt enable when set, enables a local interrupt to be generated when a change is detected on the vbus pin/ball. yes yes 0 3 suspend request interrupt enable when set, enables a local interrupt to be generated wh en a usb suspend request from the host is detected. yes yes 0 4 suspend request change interrupt enable when set, enables a local interrupt to be generated when a change in the suspend request interrupt state is detected. yes yes 0 5 resume interrupt enable when set, enables a local interrupt to be generated when a device resume is detected. yes yes 0 6 root-port reset interrupt enable when set, enables a local interrupt to be generated when a root-port reset is detected. yes yes 0 7 reserved yes n o 0
configuration registers plx technology, inc. 68 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 register 11-10. (address 22h ; locctl) local bus control bits description read write default 0 data width controls the local data bus width for ep_data accesses to endpoint buffers. to switch to 16-bit mode, write to this register us ing the lower eight data bus bits. data width does not affect accesses to other registers. values: 0 = 8 bits 1 = 16 bits yes yes 0 3:1 local clock output controls lclko pin/ba ll frequency. values: 000b = 0 (off) 001b = 3.75 mhz 010b = 7.5 mhz (default) 011b = 15 mhz 100b = 30 mhz 101b = 60 mhz 110b, 111b = reserved yes yes 010b 4 dma split bus mode when clear, i/o and dma accesses share the same data bus. when set, i/o accesses to configuration regi sters or buffers use ld[7:0], and dma accesses to buffers use ld[15:8], thereby splitting the data bus for cpu and dma accesses. yes yes 0 5 byte swap when clear, local data bus ld[15:0] is connected to the endpoint buffer with no byte swapping. when set, tw o bytes of a 16-bit data bus are swapped before connecting to the endpoint buffer. yes yes 0 7:6 buffer configuration endpoints a and b buffer configuration. for example , if value 01b is selected, endpoint a is allocated a single buffer of 1,024 bytes, while endpoint b is allocated a double buffer, two buffers of 512 bytes each. actual packets transmitted and/or receiv ed can be less than or equal to the ep_maxpkt x size for the selected endpoint. the ep_maxpkt x size must be less than or equal to the allo cated buffer size. values (in bytes): value endpoint a endpoint b 00b 512 db * 512 db 01b 1,024 512 db 10b 1,024 1,024 11b 1,024 db disabled * db is ?double-buffered.? yes yes 00b register 11-11. (address 23h; chipr ev_legacy) legacy silicon revision bits description read write default 7:0 legacy chip revision this register returns a legacy silicon revision number, for use by the net2270 firmware. note: the chip revision is encoded as a 2-digit binary-coded decimal (bcd) value. the most significa nt digit is the major revision number, and the least significant di git is the minor revision number. yes no 40h
august, 2005 main control registers net2272 local bus to usb 2.0 peripheral controller data book 69 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 register 11-12. (address 24h; locctl1) local bus control 1 bits description read write default 1:0 dma mode determines dreq behavior dur ing dma transactions. values: 00b = slow mode . dreq is de-asserted seve ral clock periods after the dma transaction starts, and re-asserted several clock periods after the dma transaction is complete. this mode is compatible with the net2270. 01b = fast mode. dreq is de-asserted when a dma transaction starts, and re-asserted soon after the dma transaction is complete. this mode provides higher dma performance. 10b = burst mode. dreq is asserted when the dma request enable bit is set and there is space and/or data av ailable in the endpoint buffer. dreq remains asserted until the buffer becomes empty or full, the dma request enable bit is cleared, eot is asserted, or ep_transfer x counts to 0 for an in endpoint. 11b = reserved yes yes 00b 2 dma dack enable when clear, the net2272 does not re cognize the dack input pin/ball. when set, the dack input pin/ball is enabled. dma dack enable is automatically set when the dmareq register dma request enable bit is set. in dma split bus mode, do not clear this bit if there is a possibility that dack can be asserted. yes yes 0 7:3 reserved yes n o 0 h register 11-13. (address 25h; chi prev_2272) net2272 silicon revision bits description read write default 7:0 chip revision this register returns the net2272 silicon revision number. note: the chip revision is encoded as a 2-digit bcd value. the most significant digit is the major revision number, and the least significant digit is the minor revision number. yes no 11h
configuration registers plx technology, inc. 70 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 8.5 usb control registers register 11-14. (address 18h; us bctl0) usb control (low byte) bits description read write default 0 reserved ye s n o 0 1 i/o wakeup enable when clear, asserting cs# does not cause a device-remote wakeup. when set, i/o wakeup enable enables cs# assertion to initiate a device-remote wakeup. ye s ye s 0 2 reserved ye s n o 0 3 usb detect enable when clear, the net2272 does not appear to be connected to the usb host. when set, the net2272 appears to be connected to the usb host. do not set usb detect enable until the configuration re gisters are programmed. when operating as a bus-powered de vice, program the registers and promptly set usb detect enable after vbus is detected. ye s ye s 0 4 reserved ye s n o 0 5 usb root-port wakeup enable when clear, the wakeup condition is not detected. when set, the root-port wakeup condition is detected when activity is detected on the usb. ye s ye s 1 7:6 reserved yes no 00b register 11-15. (address 19h; us bctl1) usb control (high byte) bits description read write default 0 vbus pin/ball indicates the vbus input pin/ball state. when se t, indicates that the net2272 is connected to the usb. ye s n o 0 1 usb full speed when set, indicates that the transceiver is operating in full-speed mode (12 mbps). ye s n o 0 2 usb high speed when set, indicates that the transc eiver is operating in high-speed mode (480 mbps). ye s n o 0 3 generate resume writing 1 causes a resume sequence to be initiated to the host if device-remote wakeup is enabled. write generate resume after a device-remote wakeup is ge nerated (cs# asserted). generate resume is self-clearing, and reading always returns a 0. no yes/resume 0 4 virtual endpoint enable when set, enables the net2272 virt ual endpoint feature. a nak is returned to the usb host if an in to ken is received for a virtual endpoint. ye s ye s 0 7:5 reserved yes no 000b
august, 2005 usb control registers net2272 local bus to usb 2.0 peripheral controller data book 71 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 register 11-16. (address 1ah; f rame0) frame counter (low byte) bits description read write default 7:0 frame[7:0] contains the frame counter from the most recent sof packet. ye s n o 0 h register 11-17. (address 1bh; f rame1) frame counter (high byte) bits description read write default 2:0 frame[10:8] contains the frame counter from the most recent sof packet. yes no 000b 7:3 reserved ye s n o 0 h register 11-18. (address 30h; ouraddr) our current usb address bits description read write default 6:0 our address contains the current device usb address. our address is cleared when a root-port reset is dete cted. after written, the register does not update until the corresponding control write transfer status transaction successfully completes. this allows the firmware to write this field when the setup packet is received, rather than waiting for a successful status transaction. refer to the usb r2.0 , sections 9.2.6.3 and 9.4.6. ye s ye s 0 h 7 force immediate if force immediate is set when this register is written, the net2272 usb address is immediately updated, without waitin g for a valid status transaction from the usb host. no yes/force 0 register 11-19. (address 31h; usbdiag) usb diagnostic bits description read write default 0 force transmit crc error when set, a crc error is forced on the next transmit ted data packet. inverting the most significant bit of the calculated crc generates the crc error. fo rc e transmit crc error is automatically cleared at the end of the next packet. yes yes/set 0 1 prevent transmit bit-stuff when set, normal bit-stuffing is suppres sed during the next transmitted data packet. this causes a bit-stuffing error when six or more consecutive bits of 1 are in the data stream. automatically cleared at the end of the next packet. yes yes/set 0 2 force receive error when set, an error is forced on the next received data packet. as a result, the packet is not acknowledged. automatically cleared at the end of the next packet. yes yes/set 0 3 reserved ye s n o 0 4 fast times when set, the frame counter operates at a fast speed, for factory chip-testing purposes only. ye s ye s 0 7:5 reserved yes no 000b
configuration registers plx technology, inc. 72 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 register 11-20. (address 32h ; usbtest) usb test modes bits description read write default 2:0 usb test mode select valid only in high-speed mode. refer to the usb r2.0 , sections 7.1.20 and 9.4.9, for further details regarding usb test mode select . values: 000b = normal operation 001b = test_j 010b = test_k 011b = test_se0_nak 100b = test_packet 101b = test_force_enable 110b, 111b = reserved note: if the net2272 is operating in hi gh-speed mode, and the usb test mode select field is set to non-zero, the net2272 is prevented from switching out of high-speed mode. yes yes 000b 7:3 reserved ye s n o 0 h register 11-21. (address 33h; xcvrdiag) transceiver diagnostic bits description read write default 1:0 reserved ye s n o ? 2 force full speed when high, the net2272 is forced into full-speed mode (12 mbps). ye s ye s 0 3 force high speed when high, the net2272 is forced into high-speed mode (480 mbps). ye s ye s 0 5:4 opmode indicates the transceiver operational state. values: 00b = normal operation 01b = non-driving 10b = disable bit-stuffing and nrzi encoding 11b = reserved ye s n o ? 7:6 linestate indicates the dm (lines tate[1]) and dp (linesta te[0]) usb data signal states. dm and dp values, respectively: 00b = se0 (single-ended zero) 01b = j state (idle) 10b = k state (resume) 11b = se1 (single-ended one) ye s n o ?
august, 2005 usb control registers net2272 local bus to usb 2.0 peripheral controller data book 73 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 register 11-22. (address 34h; vi rtout0) virtual out interrupt 0 bits description read write default 0 reserved ye s n o 0 7:1 virtual out interrupts set when the virtual endpoint enable bit is set, and a virtual endpoint received an out token that is not mapped to a physic al endpoint. bit 1 corresponds to out endpoint numb er 1, and bit 7 corresponds to out endpoint number 7. writing 1 to a bit clears that bit. ye s yes /c l r 0 h register 11-23. (address 35h; vi rtout1) virtual out interrupt 1 bits description read write default 7:0 virtual out interrupts set when the virtual endpoint enable bit is set, and a virtual endpoint received an out token that is not mapped to a physic al endpoint. bit 0 corresponds to out endpoint numb er 8, and bit 7 corresponds to out endpoint number 15. writing 1 to a bit clears that bit. ye s yes /c l r 0 h register 11-24. (address 36h; vi rtin0) virtual in interrupt 0 bits description read write default 0 reserved ye s n o 0 7:1 virtual in interrupts set when the virtual endpoint enable bit is set, and a virtual endpoint received an in token that is not mapped to a physical endpoint. bit 1 corresponds to in endpoint number 1, and bit 7 corresponds to in endpoint number 7. writing 1 to a bit clears that bit. ye s yes /c l r 0 h register 11-25. (address 37h; vi rtin1) virtual in interrupt 1 bits description read write default 7:0 virtual in interrupts set when the virtual endpoint enable bit is set, and a virtual endpoint received an in token that is not mapped to a physical endpoint. bit 0 corresponds to in endpoint number 8, and bit 7 corresponds to in endpoint number 15. writing 1 to a bit clears that bit. ye s yes /c l r 0 h
configuration registers plx technology, inc. 74 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 register 11-26. (address 40h; setup0) setup byte 0 bits description read write default 7:0 setup byte 0 provides byte 0 of the last setup pa cket received. for a standard device request, the following bmrequesttype information is returned. refer to the usb r2.0 , section 9.3. values: bit description 7 direction: 0 = host-to-device; 1 = device to host 6:5 type: 00b = standard, 01b = class, 10b = vendor, 11b = reserved 4:0 recipient: 00000b = de vice, 00001b = interface, 00010b = endpoint, 00011b = other, 04h - 31h = reserved ye s n o 0 h register 11-27. (address 41h; setup1) setup byte 1 bits description read write default 7:0 setup byte 1 provides byte 1 of the last setup pa cket received. for a standard device request, the following brequest code information is returned. refer to the usb r2.0 , section 9.4. values: 00h = get status 01h = clear feature 02h = reserved 03h = set feature 04h = reserved 05h = set address 06h = get descriptor 07h = set descriptor 08h = get configuration 09h = set configuration 0ah = get interface 0bh = set interface 0ch = synch frame yes no 00h register 11-28. (address 42h; setup2) setup byte 2 bits description read write default 7:0 setup byte 2 provides byte 2 of the last setup pa cket received. for a standard device request, the least significant byte of the wvalue field is returned. refer to the usb r2.0 , section 9.3. ye s n o 0 h register 11-29. (address 43h; setup3) setup byte 3 bits description read write default 7:0 setup byte 3 provides byte 3 of the last setup pa cket received. for a standard device request, the most signi ficant byte of the wvalue field is returned. refer to the usb r2.0 , section 9.3.3. ye s n o 0 h
august, 2005 usb control registers net2272 local bus to usb 2.0 peripheral controller data book 75 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 register 11-30. (address 44h; setup4) setup byte 4 bits description read write default 7:0 setup byte 4 provides byte 4 of the last setup pa cket received. for a standard device request, the least significant byte of the windex field is returned. refer to the usb r2.0 , section 9.3.4. ye s n o 0 h register 11-31. (address 45h; setup5) setup byte 5 bits description read write default 7:0 setup byte 5 provides byte 5 of the last setup pa cket received. for a standard device request, the most signi ficant byte of the windex field is returned. refer to the usb r2.0 , section 9.3.4. ye s n o 0 h register 11-32. (address 46h; setup6) setup byte 6 bits description read write default 7:0 setup byte 6 provides byte 6 of the last setup pa cket received. for a standard device request, the least significant byte of the wlength field is returned. refer to the usb r2.0 , section 9.3.3. ye s n o 0 h register 11-33. (address 47h; setup7) setup byte 7 bits description read write default 7:0 setup byte 7 provides byte 7 of the last setup pa cket received. for a standard device request, the most signi ficant byte of the wlength field is returned. refer to the usb r2.0 , section 9.3.3. yes no 0h
configuration registers plx technology, inc. 76 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 8.6 endpoint registers there are four sets of endpoint registers, one for each endpoint (0, a, b, and c). to access an endpoint, set the pagesel register page select field to the needed endpoint, th en read or write to an endpoint register as defined in the following register tables. status bits associated with an endpoint packet buffer (buffer full, buffer empty, and so forth), are valid only for the currently visible buffer ( that is , the buffer that is currently being written to or r ead from the local bus). note: if dma request is enabled, then register 11-34 accesses the endpoint buffer sel ected by dma endpoint select, rather than page select. register 11-34. (address 05h ; ep_data) endpoint data bits description read write default 7:0 endpoint data (low-order byte) when operating with an 8-bit bus width, bi ts [7:0] of this register provide the buffer transaction data (read or wr ite). when operating with a 16-bit bus width, bits [7:0] of this regi ster provide the low-order byte. ye s ye s 0 h 15:8 endpoint data (high-order byte) when operating with a 16-bit bus width, bi ts [15:8] of this register provide the high-order byte. ye s ye s 0 h
august, 2005 endpoint registers net2272 local bus to usb 2.0 peripheral controller data book 77 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 notes: if dma request is enabled, then the buffer full and buffer empty bits correspond to th e endpoint buffer selected by dma endpoint select, rather than page select. buffer full and buffer empty bits take up to 100 ns to become valid after an endpoint buffer is written or read. register 11-35. (addr ess 06h; ep_stat0) endpoint status (low byte) bits description read write default 0 data in token interrupt set when a data in token is received from the host. writing 1 clears this bit. ye s yes /c l r 0 1 data out token interrupt set when a data out token is received from the host. also set by ping tokens (high-speed mode onl y). writing 1 clears this bit. ye s yes /c l r 0 2 data packet transmitted interrupt set when a data packet is transmi tted from the endpoint to the host. writing a 1 clears this bit. ye s yes /c l r 0 3 data packet received interrupt set when a data packet is received from the host. writing 1 clears this bit. ye s yes /c l r 0 4 short packet transferred interrupt set when the length of the last packet was less than the maximum packet size ( ep_maxpkt x ). writing 1 clears this bit. ye s yes /c l r 0 5 nak out packets set when a short data packet is received from the host, and the ep_rspset register nak out packets mode bit is set. writing 1 clears this bit. while this bit is set, s ubsequent out packet s are acknowledged with a nak handshake. nak out packets can also be controlled by the ep_rspclr and ep_rspset registers. ye s yes /c l r 0 6 buffer empty for an in endpoint, a buffer is avai lable to the local bus for writing up to maxpkt bytes. for an out endpoint, the currently se lected buffer has a count of 0, or no buffer is available on the local bus (nothing to read). ye s n o 1 7 buffer full set when the endpoint packet buffer is full. for an in endpoint, the currently selected buffer has a count of maxpkt by tes, or no buffer is available to the local bus for writing (no space to write). for an out endpoint, there is a buffer available on the local bus, and there are maxpkt bytes available to read (entire packet is available for reading). ye s n o 0
configuration registers plx technology, inc. 78 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 register 11-36. (addr ess 07h; ep_stat1) endpoint status (high byte) bits description read write default 0 timeout for an in endpoint, the last usb pa cket transmitted was not acknowledged by the host pc, indicating a bus error. the host pc expects the same packet to be re-transmitted in response to the next in token. for an out endpoint, the last usb packet received contained a crc or bit-stuffing error, and was not acknowledged by the net2272. the host pc re-transmits the packet. writing 1 clears this bit. ye s yes /c l r 0 1 usb out ack transmitted the last usb out data packet transf erred was successfully acknowledged with an ack to the host. writing 1 clears this bit. ye s yes /c l r 0 2 usb out nak transmitted the last usb out data packet was not accepted, but was acknowledged with a nak to the host. writing 1 clears this bit. ye s yes /c l r 0 3 usb in ack received the last usb in data packet transf erred was successfully acknowledged with an ack from the host. writing 1 clears this bit. ye s yes /c l r 0 4 usb in nak transmitted the last usb in packet was not pr ovided, but was acknowledged with a nak. writing 1 clears this bit. ye s yes /c l r 0 5 usb stall transmitted the last usb packet was not accepted or provided because the endpoint was stalled, but was acknowledged with a stall. writing 1 clears this bit. ye s yes /c l r 0 6 local out zlp when set, indicates that the current local buffer contains a zero-length packet. ye s n o 0 7 buffer flush writing 1 to this bit causes the pa cket buffer to be flushed and the corresponding ep_avail x register to be cleared. buffer flush is self-clearing and always written after an endpoint configuration ( such as direction, address) is changed. do not assert during dma split bus mode if the page select field is selecti ng another endpoint. no yes/flush 0 register 11-37. (address 08h; ep_transfer0 ) in endpoint tran sfer count (byte 0) bits description read write default 7:0 ep_transfer[7:0] for in endpoints, determin es the number of bytes to transmit to the host. write before packet data is written to the buffer. when the count reaches 0, remaining buffer data is validated. writing 0 to ep_transfer0 when ep_transfer1 and ep_transfer2 have a value of 0 validates th e buffer contents, regardless of the auto validate bit state. if the buffer is empty, writing 0 to ep_transfer0 validates a zero-length packet. note: validation takes approximately 100 ns. for out endpoints, counter is cleared when the nak out packets bit is cleared ( ep_rspclr , bit 7). this counter is incremented for every byte read from the packet buffer. if 16-bit mode is selected , and only one of the two bytes is valid, the counter increments only by 1. ye s ye s 0 h
august, 2005 endpoint registers net2272 local bus to usb 2.0 peripheral controller data book 79 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 register 11-38. (address 09h; ep_transfer1 ) in endpoint tran sfer count (byte 1) bits description read write default 7:0 ep_transfer [15:8] refer to register 11-37 for description. ye s ye s 0 h register 11-39. (address 0ah; ep_transfe r2) in endpoint tran sfer count (byte 2) bits description read write default 7:0 ep_transfer [23:16] refer to register 11-37 for description. ye s ye s 0 h register 11-40. (address 0bh; ep_i rqenb) endpoint interrupt enable bits description read write default 0 data in token interrupt enable when set, enables a local interrupt to be set when a data in token is received from the host. ye s ye s 0 1 data out token interrupt enable when set, enables a local interrupt to be set when a data out token is received from the host. ye s ye s 0 2 data packet transmitted interrupt enable when set, enables a local interrupt to be set when a data packet is transmitted to the host. ye s ye s 0 3 data packet received interrupt enable when set, enables a local interrupt to be set when a data packet is received from the host. ye s ye s 0 4 short packet transferred interrupt enable when set, enables a local interrupt to be set when a short data packet is transferred to and/or from the host. ye s ye s 0 7:5 reserved yes no 000b
configuration registers plx technology, inc. 80 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 note: if dma request is enabl ed, then the value in register 11-41 corresponds to the endpoint buffer selected by dma endpoint select, rather than page select. register 11-41. (address 0c h; ep_avail0) endpoint a vailable count (low byte) bits description read write default 7:0 ep_avail[7:0] for in endpoints, returns the number of empty bytes in the packet buffer. values range from 0 (full) to 1,024 (empty) bytes. ep_avail[7:0] is updated after 2 bytes are written to the buffer, or when the buffer is validated. for out endpoints, returns the number of valid bytes in the endpoint packet buffer. values range from 0 (empty) to 1,024 (full) bytes. if only the low byte of ep_avail[7:0] is read, the entire 11-bit field is frozen until the upper byte is read. ye s n o 0 h register 11-42. (address 0d h; ep_avail1) endpoint a vailable count (high byte) bits description read write default 2:0 ep_avail[10:8] refer to register 11-41 for description. yes no 000b 7:3 reserved ye s n o 0 h
august, 2005 endpoint registers net2272 local bus to usb 2.0 peripheral controller data book 81 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 note: writing 1 to bits [7:0] clears the corresponding register bits. register 11-43. (add ress 0eh; ep_rspclr) endpoint response clear bits description read write default 0 endpoint halt used to clear the endpoint stall bit. when an endpoint set feature standard request to the halt bit is detected by the local cpu, the local cpu must write 1 to endpoint halt. reading this bit returns the endpoint halt bit current state. for endpoint 0, the halt bit is automatically cleared when another setup packet is re ceived. for endpoint 0, the control status stage handshake bit should be cleared when the endpoint halt bit is set. writing a 1 to this bit also clears the endpoint toggle bit. ye s yes /c l r 0 1 endpoint toggle used to clear the endpoint data toggle bit. (refer to the usb r2.0 , section 8.6.) reading endpoint toggle returns the endpoint data toggle bit current state. under normal operati on, the toggle bit is automatically controlled; therefore, the loca l cpu need not use this bit. endpoint toggle is also cleared when the endpoint halt bit is cleared. ye s yes /c l r 0 2 nak out packets mode used only for out endpoints. when nak out packets mode is true, the nak out packets bit is set whenever nak out packets mode receives a short packet. ye s yes /c l r 1 3 control status stage handshake used only for endpoint 0. automatically set when a setup packet is detected. while the bit is set, a cont rol status stage is acknowledged with a nak. when cleared, returns the pr oper response to the host (ack for control reads, and zero-length packets for control writes). ye s yes /c l r 0 4 interrupt mode used for interrupt endpoint s. for normal interrupt data, set to 0 and follow standard data toggl e protocol. when interrupt mode is used for isochronous rate feedback information, set high. in this mode, the data toggle bit is changed after each packet is transm itted to the host without regard to handshaking. (refer to section 5.6.4.1 and section 5.6.4.2 .) no packet retries are performed in rate feedback mode. ye s yes /c l r 0 5 auto validate when set, allows automatic validation of maximum-size packets. that is , there are ep_maxpkt x bytes in the endpoint buffer, and the data is returned to the usb host in response to the next in token without being manually validated by the local cpu. this is the normal operation mode for endpoint transactions and the default state for this bit. when cleared, packets must be ma nually validated. ye s yes /c l r 1 6 hide status stage when set, the following bits are not set for status stage packets: data in token interrupt, data out to ken interrupt, data packet received interrupt , data packet transmitted interrupt , short packet transferred interrupt, usb out ack transmitted, usb out nak transmitted, usb in ack received, and usb in nak transmitted. hide status stage is not used for normal operati on ? it is intended for special applications, as determ ined by the designer. ye s yes /c l r 0 7 alt nak out packets set when a short data pa cket is received from th e host by this endpoint, and nak out packets mode bit is set. if alt nak out packets is set and another out token is received, a nak is returned to the host if another out packet is transmitted to this e ndpoint. can also be cleared by the ep_stat0 register nak out packets bit. ye s yes /c l r 0
configuration registers plx technology, inc. 82 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 notes: writing 1 to bits [7:0] sets the corresponding register bits. refer to register 11-43 for bit descriptions. register 11-44. (address 0fh; ep_rspset) endpoint response set bits description read write default 0 endpoint halt yes yes/set 0 1 endpoint toggle yes yes/set 0 2 nak out packets mode yes yes/set 1 3 control status stage handshake yes yes/set 0 4 interrupt mode yes yes/set 0 5 auto validate yes yes/set 1 6 hide status stage yes yes/set 0 7 alt nak out packets yes yes/set 0 register 11-45. (address 28h ; ep_maxpkt0) endpoint maximum packet size (low byte) bits description read write default 7:0 ep_maxpkt[7:0] determines endpoint ma ximum packet size. ye s ye s ep0 = 64 epa = 512 epb = 512 epc = 512 register 11-46. (address 29h ; ep_maxpkt1) endpoint maxi mum packet size (high byte) bits description read write default 2:0 ep_maxpkt[10:8] determines endpoint ma ximum packet size. ye s ye s ep0 = 64 epa = 512 epb = 512 epc = 512 4:3 additional transaction opportunities determines the number of additi onal transaction opportunities per microframe for high-speed isochronous and interrupt endpoints. values: 00b = none (one transa ction per microframe) 01b = one additional (two per microframe) 10b = two additional (t hree per microframe) 11b = reserved yes yes 00b 7:5 reserved yes no 000b
august, 2005 endpoint registers net2272 local bus to usb 2.0 peripheral controller data book 83 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 note: for endpoint 0, all fields in register 11-47 , except endpoint direction, are assigned to fixed values, and are reserved . register 11-47. (address 2ah; ep_cfg) endpoint configuration bits description read write default 3:0 endpoint number selects the endpoint number. valid numbers are 0 to 15. endpoint number has no effect on endpoi nt 0, which always retains an endpoint number of 0. ye s ye s 0 h 4 endpoint direction chooses the endpoint direction selected by the page select field. ep_dir = 0 defines host out to devi ce, while ep_dir = 1 defines host in from device. endpoint 0 is bi-directional, and uses endpoint direction for a test mode. when set, endpoint packet buffers can be read for diagnostics. for endpoint 0, endpoint direction is dynamic, and depe nds on the direction bit in the last setup packet. note: a maximum of one out and in endpoint is allowed for each endpoint number. ye s ye s 0 6:5 endpoint type selects endpoint type. end point 0 is forced to a control type. values: 00b = reserved 01b = isochronous 10b = bulk 11b = interrupt yes yes 00b 7 endpoint enable when set, enables endpoint. has no effe ct on endpoint 0, which is always enabled. when cleared, does not re ad as a 0 until all pending usb transactions on the endpoint are complete. ye s ye s 0 register 11-48. (address 2bh; ep_hbw) endpoint high bandwidth bits description read write default 1:0 high-bandwidth out transaction pid provides the pid of the last high bandw idth out packet received. this field is stable when the data packet received interrupt bit is set, and remains stable until another out pa cket is received, which is based on the currently active buffer. values: 00b = data0 01b = data1 10b = data2 11b = mdata yes no 00b 7:2 reserved ye s n o 0 h
configuration registers plx technology, inc. 84 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 notes: in packets move from lcl ? va l i d ? usb ? free out packets move from usb ? va l i d ? lcl ? free if an endpoint is double-buffered, the buffers are never in the same state. if an endpoint is single-buffered, the unused (b) buffer is locked into the buff_free state. register 11-49. (address 2ch; ep_b uff_states) endpoi nt buffer states bits description read write default 1:0 buffer a state provides the current endpoint buffer a state. values: 00b = buff_free ? buffer empty, free to assign 01b = buff_valid ? buffer has valid packet, waiting to move to local bus or usb host 10b = buff_lcl ? buffer assigned to local bus 11b = buff_usb ? buffer assigned to usb host ye s n o ? 3:2 buffer b state provides the current endpoint buffer b state. values: 00b = buff_free ? buffer is empty, free to assign 01b = buff_valid ? buffer has valid packet, waiting to move to local bus or usb host 10b = buff_lcl ? buffer assigned to local bus 11b = buff_usb ? buffer assigned to usb host ye s n o ? 7:4 reserved ye s n o 0 h
august, 2005 net2272 register differences from net2270 registers net2272 local bus to usb 2.0 peripheral controller data book 85 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 8.7 net2272 register differences from net2270 registers table 8-5 lists the net2272 register additions and removal from the net2270 registers. table 8-5. net2272 register differences from net2270 registers bits registers additions ep_stat1 [6] local out zlp status irqenb0 [4] virtual endpoint interrupt enable irqstat0 [4] virtual endpoint interrupt status locctl1 [1:0] dma mode usbctl1 [4] virtual endpoint enable ep_buff_states endpoint buffer states ep_hbw endpoint high bandwidth locctl1 local bus control 1 virtin0 virtual in interrupt 0 virtin1 virtual in interrupt 1 virtout0 virtual out interrupt 0 virtout1 virtual out interrupt 1 removal usbdiag [5] force bi-directional to inputs ?
configuration registers plx technology, inc. 86 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91
net2272 local bus to usb 2.0 peripheral controller data book 87 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 chapter 9 usb standard device requests 9.1 overview standard device requests must be supported by endpoint 0. (refer to the usb r2.0 , chapter 9.) the local bus cpu decodes the setup packets for endpoint 0 and generates a response, based on the information in the following tables. table 9-1. standard request codes brequest value get_status 0h clear_feature 1h reserved 2h set_feature 3h reserved 4h set_address 5h get_descriptor 6h set_descriptor 7h get_configuration 8h set_configuration 9h get_interface ah set_interface bh synch_frame ch table 9-2. descriptor types descriptor type value device 1h configuration 2h string 3h interface 4h endpoint 5h device qualifier 6h other_speed_configuration 7h interface power 8h
usb standard device requests plx technology, inc. 88 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 9.2 control write transfers note: the local cpu must write the new device address into the usbaddr configuration register. note: the local cpu must keep trac k of the configuration value. note: the local cpu must keep tr ack of the interface value. note: the local cpu must keep track of th e device-remote wakeup enable state. table 9-3. set address (0 bytes) offset number of bytes description recommended value ? 0 sets usb addres s of device. va l u e s : wvalue = device address windex = 0 wlength = 0 ? table 9-4. set configuration (0 bytes) offset number of bytes description recommended value ? 0 sets device configuration. values: wvalue = configuration value windex = 0 wlength = 0 ? table 9-5. set interface (0 bytes) offset number of bytes description recommended value ? 0 selects alternate setting for specified interface. values: wvalue = alternate setting windex = specified interface wlength = 0 ?
august, 2005 control write transfers net2272 local bus to usb 2.0 peripheral controller data book 89 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 table 9-6. device clear feature (0 bytes) offset number of bytes description recommended value ? 0 clear the selected device feature. values: wvalue = feature selector windex = 0 wlength = 0 fs = 1 ? device-remote wakeup (disable) ? table 9-7. device set feature (0 bytes) offset number of bytes description recommended value ? 0 set the selected device feature. va l u e s : wvalue = feature selector wlength = 0 windex va l u e s : fs = 1 ? device-remote wakeup (enable), windex = 0 fs = 2 ? test mode, windex = specifies test mode ? table 9-8. endpoint set feature (0 bytes) offset number of bytes description recommended value ? 0 set the selected endpoint feature. va l u e s : wvalue = feature selector windex = endpoint number wlength = 0 fs = 0 ? endpoint halt (sets endpoint halt bit) note: the local cpu must set the endpoint halt bit by writing to the ep_rspset register endpoint halt bit. ? table 9-9. endpoint clear feature (0 bytes) offset number of bytes description recommended value ? 0 clear the selected endpoint feature. va l u e s : wvalue = feature selector windex = endpoint number wlength = 0 fs = 0 ? endpoint halt (clears endpoint halt bit) note: the local cpu must clear the endpoint halt bit by writing to the ep_rspclr register endpoint halt bit. ?
usb standard device requests plx technology, inc. 90 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 9.3 control read transfers table 9-10. get device status (2 bytes) offset number of bytes description recommended value 0h 2 bits description 0= power supply good in self-powered mode 1 = device-remote wakeup enabled [15:2] = reserved determined by local cpu table 9-11. get interface status (2 bytes) offset number of bytes description recommended value 0h 2 bits [15:0] = reserved 0000h table 9-12. get endpoint status (2 bytes) offset number of bytes description recommended value 0h 2 bits description 0 = endpoint halted [15:1] = reserved determined by local cpu table 9-13. get device descriptor (18 bytes) offset number of bytes description recommended value 0h 1 length 12h 1h 1 type (device) 01h 2h 2 usb r2.0 release number 0200h 4h 1 class code ffh 5h 1 sub class code 00h 6h 1 protocol 00h 7h 1 maximum endpoint 0 packet size 40h 8h 2 vendor id 0525h 10h 2 product id 2272h 12h 2 device release number 0110h 14h 1 index of string descriptor describing manufacturer 01h 15h 1 index of string descri ptor describing product 02h 16h 1 index of string descriptor descri bing serial number 00h (not enabled) 17h 1 number of configurations determined by local cpu
august, 2005 control read transfers net2272 local bus to usb 2.0 peripheral controller data book 91 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 table 9-14. get device qualifier (10 bytes) offset number of bytes description recommended value 0h 1 length 0ah 1h 1 type (device qualifier) 06h 2h 2 usb r2.0 release number 0200h 4h 1 class code ffh 5h 1 sub class code 00h 6h 1 protocol 00h 7h 1 maximum endpoint 0 packet size for other speed 40h 8h 1 number of other- speed configurations determined by local cpu 9h 1 reserved 00h
usb standard device requests plx technology, inc. 92 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 9.3.1 get other_speed_configuration descriptor the structure of othe r_speed_configuration is identical to a configuration descriptor, except that the bdescriptortype is 7 instead of 2. 9.3.2 get configuration descriptor the net2272 supports a variety of configurations, interfaces, and endpoints, each of which is defined by the descriptor data returned to the usb host. th e local cpu is responsible for providing this data to the net2272 when requested by the host. the following example contains one configuration, a nd two interfaces: the first interface defines one bulk out endpoi nt at address 1 with a full-speed maximum packet size of 512 bytes and one interrupt in endpoint at address 82h (endpoint number = 2) with a maximum packet size of 8 bytes. the second interface defines one bulk out endpoi nt at address 3 with a maximum packet size of 512 bytes. note: all interface and endpoint descriptors are returned in response to a get configuration descriptor request, and for this example, 48 bytes are returned.
august, 2005 get configuration descriptor net2272 local bus to usb 2.0 peripheral controller data book 93 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 table 9-15. get configuration descriptor offset number of bytes description recommended value configuration descriptor 0h 1 length 09h 1h 1 type (configuration) 02h 2h 2 total length returned for this configuration 0030h 4h 1 number of interfaces 02h 5h 1 number of this configuration 01h 6h 1 index of string descriptor de scribing this configuration 00h 7h 1 attributes bits description [4:0] = reserved 5 = device-remote wakeup 6= self-powered 7= 1 determined by local cpu 8h 1 maximum usb power required (in 2 ma units) determined by local cpu interface 0 descriptor 0h 1 descriptor size, in bytes 09h 1h 1 type (interface) 04h 2h 1 number of this interface 00h 3h 1 alternate interface 00h 4h 1 number of endpoints this interf ace uses (excluding endpoint 0) 02h 5h 1 class code ffh 6h 1 sub class code 00h 7h 1 device protocol 00h 8h 1 index of string descriptor describing this interface 00h continued ?
usb standard device requests plx technology, inc. 94 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 bulk out endpoint 1 descriptor 0h 1 descriptor size 07h 1h 1 descriptor type (endpoint) 05h 2h 1 endpoint address bits description [3:0] = endpoint number [6:4] = reserved 7 = direction (1 = in, 0 = out) 01h 3h 1 endpoint attributes bits description [1:0] values: 00b = control 01b = isochronous 10b = bulk 11b = interrupt [7:2] = reserved 02h 4h 2 bits [10:0] = maximum endpoint packet size 0200h (hs) 6h 1 maximum endpoint nak rate determined by local cpu interrupt in endpoint 2 descriptor 0h 1 descriptor size 07h 1h 1 descriptor type (endpoint) 05h 2h 1 endpoint address bits description [3:0] = endpoint number [6:4] = reserved 7 = direction (1 = in, 0 = out) 82h 3h 1 endpoint attributes bits description [1:0] values: 00b = control 01b = isochronous 10b = bulk 11b = interrupt [7:2] = reserved 03h 4h 2 bits [10:0] = maximum endpoint packet size 0008h 6h 1 interval for polling endpoint determined by local cpu continued ? table 9-15. get configuration descriptor (cont.) offset number of bytes description recommended value
august, 2005 get configuration descriptor net2272 local bus to usb 2.0 peripheral controller data book 95 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 interface 1 descriptor 0h 1 descriptor size, in bytes 09h 1h 1 type (interface) 04h 2h 1 number of this interface 01h 3h 1 alternate interface 00h 4h 1 number of endpoints this interf ace uses (excluding endpoint 0) 01h 5h 1 class code ffh 6h 1 sub class code 00h 7h 1 device protocol 00h 8h 1 index of string descriptor describing this interface 00h bulk out endpoint 3 descriptor 0h 1 descriptor size 07h 1h 1 descriptor type (endpoint) 05h 2h 1 endpoint address bits description [3:0] = endpoint number [6:4] = reserved 7 = direction (1 = in, 0 = out) 03h 3h 1 endpoint attributes bits description [1:0] values: 00b = control 01b = isochronous 10b = bulk 11b = interrupt [7:2] = reserved 02h 4h 2 bits [10:0] = maximum endpoint packet size 0200h 6h 1 maximum endpoint nak rate determined by local cpu table 9-16. get string descriptor 0 (4 bytes) offset number of bytes description recommended value 0h 1 descriptor size, in bytes 04h 1h 1 descriptor type (string) 03h 2h 2 language id (english = 09h, u.s. = 04h) 0409h table 9-15. get configuration descriptor (cont.) offset number of bytes description recommended value
usb standard device requests plx technology, inc. 96 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 table 9-17. get string descriptor 1 (30 bytes) offset number of bytes description recommended value 0h 1 descriptor size, in bytes 1eh 1h 1 descriptor type (string) 03h 2h 28 manufacturer descriptor (text string is encoded in unicode) ?plx technology? table 9-18. get string descriptor 2 (66 bytes) offset number of bytes description recommended value 0h 1 descriptor size, in bytes 42h 1h 1 descriptor type (string) 03h 2h 64 product descriptor (text string is encoded in unicode) ?net2272 usb peripheral controller? table 9-19. get string descriptor 3 (10 bytes) offset number of bytes description recommended value 0h 1 descriptor size, in bytes 0ah 1h 1 descriptor type (string) 03h 2h 8 serial number descriptor (text string is encoded in unicode) 1001h table 9-20. get configuration (1 byte) offset number of bytes description recommended value 0h 1 returns current device configuration 00h or currently selected configuration table 9-21. get interface (1 byte) offset number of bytes description recommended value 0h 1 returns current alternate setting for the specified interface 00h or currently selected interface
net2272 local bus to usb 2.0 peripheral controller data book 97 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 chapter 10 nand tree test 10.1 nand tree the vbus pin/ball is the input to the nand tree, and the output is observed on the lclko pin/ball. the vbus pin/ball is inverted into the nand tree; therefore, hold vbus low while the other pins/balls are being tested. the nand gates are tied together, with each output f eeding the input of the next. a walking zeros pattern is then applied to the net2272 pins/b alls. all pins/balls are initially set to logic one (except vbus), and a logic zero is then walked (asserted) on each input in succession, while all other inputs remain at logic one. the net result of this pattern is a series of alternating ones and zeros that are observed on the lclko pin/ball. failure to observe the alternating pattern indicates a connectivity failure between the input pin/ball and asic bonding pad for the corresponding pattern location. 10.2 nand tree connections enable the nand tree by setting the test, la3, and la4 pins/balls high. this also forces all bi-directional pins/balls to the input direction. the nand tree connection sequence is as follows: 1. vbus (input, inverted) 2. cs#, iow#, ior#, reset#, ale, eot, dack , dmard#, ld15, ld14, ld13, ld12, ld11, ld10, ld9, ld8, ld7, ld6, ld5, ld4, ld3, ld2, ld1, ld0, dmawr#, la0, la1, la2 3. lclko (output)
nand tree test plx technology, inc. 98 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91
net2272 local bus to usb 2.0 peripheral controller data book 99 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 chapter 11 electrical specifications 11.1 absolute maximum ratings warning: conditions that ex ceed the absolute maximum li mits can destroy the device. table 11-1. absolute maximum ratings symbol parameter conditions min max unit avdd, pvdd, vdd25, vddc 2.5v supply voltages with respect to ground -0.5 +3.6 v vdd33 3.3v supply voltage with respect to ground -0.5 +4.6 v vddio i/o supply voltage with respect to ground -0.5 +4.6 v v i dc input voltage 3.3v buffer -0.5 +4.6 v 5v tolerant buffer -0.5 +6.6 v i out dc output current (per pin/ball) 3 ma buffer -10 +10 ma 6 ma buffer -20 +20 ma 12 ma buffer -40 +40 ma t stg storage temperature no bias -65 +150 c t amb ambient temperature under bias 0 +85 c v esd esd rating r = 1.5k ohms, c = 100 pf ? 2 kv
electrical specifications plx technology, inc. 100 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.2 recommended operating conditions warning: conditions that exceed the operating limits can cause the net2272 to incorrectly function. table 11-2. recommended operating conditions symbol parameter conditions min max unit avdd, pvdd, vdd25, vddc 2.5v supply voltages 2.2 2.6 v vdd33 3.3v supply voltage 3.2 3.5 v vddio i/o supply voltage 1.7 3.5 v v n negative trigger voltage 3.3v buffer 0.8 1.7 v 5v tolerant buffer 0.8 1.7 v v p positive trigger voltage 3.3v buffer 1.3 2.4 v 5v tolerant buffer 1.3 2.4 v v il low-level input voltage 3.3v buffer 0 0.7 v 5v tolerant buffer 0 0.8 v v ih high-level input voltage 3.3v buffer 0.5 * vddio vddio v 5v tolerant buffer 2.0 5.5 v i ol low-level output current 3 ma buffer (v ol = 0.4) ? 3 ma 6 ma buffer (v ol = 0.4) ? 6 ma 12 ma buffer (v ol = 0.4) ? 12 ma i oh high-level output current 3 ma buffer (v oh = 2.4) ? -3 ma 6 ma buffer (v oh = 2.4) ? -6 ma 12 ma buffer (v oh = 2.4) ? -12 ma t a operating temperature com mercial temperature 0 85 c t r input rise times normal input 0 200 ns t f input fall time 0 200 ns t r input rise times schmitt trigger input 010ms t f input fall time 0 10 ms
august, 2005 dc specifications net2272 local bus to usb 2.0 peripheral controller data book 101 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.3 dc specifications 11.3.1 1.8v vddio co re dc specifications operating conditions ? v ddc = 2.37 to 2.63v, v ddio = 1.71 to 1.89v, v dd33 = 3.13 to 3.47v, t a = 0 to 85c typical values ? v ddc = 2.5v, v ddio = 1.8v, v dd33 = 3.3v, t a = 25c table 11-3. 1.8v vddio ? disconnected from usb (net2272 still active) symbol parameter test conditions min typ max unit i vddio 1.8v i/o supply current vddio = 1.8v 467 760 a i vddc , i vdd25 , i pvdd , i av d d 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 37 45 ma i vdd33 3.3v supply current vdd33 = 3.3v 0.08 0.1 a table 11-4. 1.8v vddio ? connected to usb (high speed) symbol parameter test conditions min typ max unit i vddio 1.8v i/o supply current vddio = 1.8v 467 760 a i vddc , i vdd25 , i pvdd , i av d d 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 52.3 58 ma i vdd33 3.3v supply current vdd33 = 3.3v 1.7 2 ma table 11-5. 1.8v vddio ? active (high speed) symbol parameter test conditions min typ max unit i vddio 1.8v i/o supply current vddio = 1.8v 700 1200 a i vddc , i vdd25 , i pvdd , i av d d 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 53.7 61 ma i vdd33 3.3v supply current vdd33 = 3.3v 5.46 6 ma table 11-6. 1.8v vddio ? connected to usb (full speed) symbol parameter test conditions min typ max unit i vddio 1.8v i/o supply current vddio = 1.8v 467 760 a i vddc , i vdd25 , i pvdd , i av d d 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 35.6 45 ma i vdd33 3.3v supply current vdd33 = 3.3v 1.5 2 ma
electrical specifications plx technology, inc. 102 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 table 11-7. 1.8v vddio ? active (full speed) symbol parameter test conditions min typ max unit i vddio 1.8v i/o supply current vddio = 1.8v 508 810 a i vddc , i vdd25 , i pvdd , i avdd 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 36.3 47 ma i vdd33 3.3v supply current vdd33 = 3.3v 5.32 6 ma table 11-8. 1.8v vddio ? suspended (connected to usb) 1 1. to prevent leakage current, 16-bit data bus (ld[15:0]) should not float when suspended. symbol parameter test conditions min typ max unit i vddio 1.8v i/o supply current vddio = 1.8v 0.07 0.1 a i vddc , i vdd25 , i pvdd , i avdd 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 0.16 31.05 a i vdd33 3.3v supply current vdd33 = 3.3v 201.9 202 a table 11-9. 1.8v vddio ? suspended (disconnected from usb) 1 1. to prevent leakage current, 16-bit data bus (ld[15:0]) should not float when suspended. symbol parameter test conditions min typ max unit i vddio 1.8v i/o supply current vddio = 1.8v 0.07 0.1 a i vddc , i vdd25 , i pvdd , i avdd 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 0.16 37.26 a i vdd33 3.3v supply current vdd33 = 3.3v 0.08 0.1 a
august, 2005 2.5v vddio power supply requirements net2272 local bus to usb 2.0 peripheral controller data book 103 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.3.2 2.5v vddio power supply requirements operating conditions ? v ddc = 2.37 to 2.63v, v ddio = 2.37 to 2.63v, v dd33 = 3.13 to 3.47v, t a = 0 to 85c typical values ? v ddc = 2.5v, v ddio = 2.5v, v dd33 = 3.3v, t a = 25c table 11-10. 2.5v vddio ? disconnected from usb (net2272 still active) symbol parameter test conditions min typ max unit i vddio 2.5v i/o supply current vddio = 2.5v 678 900 a i vddc , i vdd25 , i pvdd , i av d d 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 37 45 ma i vdd33 3.3v supply current vdd33 = 3.3v 0.08 0.1 a table 11-11. 2.5v vddio ? connected to usb (high speed) symbol parameter test conditions min typ max unit i vddio 2.5v i/o supply current vddio = 2.5v 678 900 a i vddc , i vdd25 , i pvdd , i av d d 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 52.3 58 ma i vdd33 3.3v supply current vdd33 = 3.3v 1.7 2 ma table 11-12. 2.5v vddio ? active (high speed) symbol parameter test conditions min typ max unit i vddio 2.5v i/o supply current vddio = 2.5v 1.2 2 ma i vddc , i vdd25 , i pvdd , i av d d 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 54.3 62 ma i vdd33 3.3v supply current vdd33 = 3.3v 5.46 6 ma table 11-13. 2.5v vddio ? connected to usb (full speed) symbol parameter test conditions min typ max unit i vddio 2.5v i/o supply current vddio = 2.5v 403 900 a i vddc , i vdd25 , i pvdd , i av d d 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 35.6 45 ma i vdd33 3.3v supply current vdd33 = 3.3v 1.5 2 ma
electrical specifications plx technology, inc. 104 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 table 11-14. 2.5v vddio ? active (full speed) symbol parameter test conditions min typ max unit i vddio 2.5v i/o supply current vddio = 2.5v 870 1250 a i vddc , i vdd25 , i pvdd , i avdd 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 36.3 47 ma i vdd33 3.3v supply current vdd33 = 3.3v 5.6 6 ma table 11-15. 2.5v vddio ? suspended (connected to usb) 1 1. to prevent leakage current, 16-bit data bus (ld[15:0]) should not float when suspended. symbol parameter test conditions min typ max unit i vddio 2.5v i/o supply current vddio = 2.5v 0.07 0.1 a i vddc , i vdd25 , i pvdd , i avdd 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 0.13 1 a i vdd33 3.3v supply current vdd33 = 3.3v 201.9 202 a table 11-16. 2.5v vddio ? suspended (disconnected from usb) 1 1. to prevent leakage current, 16-bit data bus (ld[15:0]) should not float when suspended. symbol parameter test conditions min typ max unit i vddio 2.5v i/o supply current vddio = 2.5v 0.07 0.1 a i vddc , i vdd25 , i pvdd , i avdd 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 0.13 1 a i vdd33 3.3v supply current vdd33 = 3.3v 0.08 0.1 a
august, 2005 3.3v vddio power supply requirements net2272 local bus to usb 2.0 peripheral controller data book 105 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.3.3 3.3v vddio power supply requirements operating conditions ? v ddc = 2.37 to 2.63v, v ddio = 3.2 to 3.5v, v dd33 = 3.13 to 3.47v, t a = 0 to 85c typical values ? v ddc = 2.5v, v ddio = 3.3v, v dd33 = 3.3v, t a = 25c table 11-17. 3.3v vddio ? disconnected from usb (net2272 still active) symbol parameter test conditions min typ max unit i vddio 3.3v i/o supply current vddio = 3.3v 1.16 1.6 ma i vddc , i vdd25 , i pvdd , i av d d 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 37 45 ma i vdd33 3.3v supply current vdd33 = 3.3v 0.08 0.1 a table 11-18. 3.3v vddio ? connected to usb (high speed) symbol parameter test conditions min typ max unit i vddio 3.3v i/o supply current vddio = 3.3v 1.12 2.8 ma i vddc , i vdd25 , i pvdd , i av d d 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 52.3 58 ma i vdd33 3.3v supply current vdd33 = 3.3v 1.7 2 ma table 11-19. 3.3v vddio ? active (high speed) symbol parameter test conditions min typ max unit i vddio 3.3v i/o supply current vddio = 3.3v 1.5 4.1 ma i vddc , i vdd25 , i pvdd , i av d d 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 53.7 62 ma i vdd33 3.3v supply current vdd33 = 3.3v 3.75 5.2 ma table 11-20. 3.3v vddio ? connected to usb (full speed) symbol parameter test conditions min typ max unit i vddio 3.3v i/o supply current vddio = 3.3v 1.12 2.8 ma i vddc , i vdd25 , i pvdd , i av d d 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 35.6 45 ma i vdd33 3.3v supply current vdd33 = 3.3v 1.5 2 ma
electrical specifications plx technology, inc. 106 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 table 11-21. 3.3v vddio ? active (full speed) symbol parameter test conditions min typ max unit i vddio 3.3v i/o supply current vddio = 3.3v 1.24 3.9 ma i vddc , i vdd25 , i pvdd , i avdd 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 36.3 47 ma i vdd33 3.3v supply current vdd33 = 3.3v 4.96 5.8 ma table 11-22. 3..3v vddio ? suspended (connected to usb) 1 1. to prevent leakage current, 16-bit data bus (ld[15:0]) should not float when suspended. symbol parameter test conditions min typ max unit i vddio 3.3v i/o supply current vddio = 3.3v 1.48 1.6 a i vddc , i vdd25 , i pvdd , i avdd 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 0.13 1 a i vdd33 3.3v supply current vdd33 = 3.3v 201.9 202 a table 11-23. 3.3v vddio ? suspended (disconnected from usb) 1 1. to prevent leakage current, 16-bit data bus (ld[15:0]) should not float when suspended. symbol parameter test conditions min typ max unit i vddio 3.3v i/o supply current vddio = 3.3v 1.48 1.6 a i vddc , i vdd25 , i pvdd , i avdd 2.5v core supply current vddc, vdd25, pvdd, avdd = 2.5v 0.13 1 a i vdd33 3.3v supply current vdd33 = 3.3v 0.08 0.1 a
august, 2005 usb full- and high-speed dc specifications net2272 local bus to usb 2.0 peripheral controller data book 107 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.3.4 usb full- and high -speed dc specifications operating conditions ? vddc = 2.2 to 2.6v, vddio = 1.7 to 3.5v, t a = 0 to 85c typical values ? vddc = 2.5v, vddio = 3.3v, t a = 25c table 11-24. usb full-speed dc specifications symbol parameter conditions min typ max unit v ih input high level (driven) note 4 2.0 ? ? v v ihz input high level (floating) note 4 2.7 ? 3.6 v v il input low level note 4 ? ? 0.8 v v di differential input sensitivity | (d+) - (d-) | 0.2 ? ? v v cm differential common mode range includes v di range 0.8 ? 2.5 v v ol output low level notes 4 , 5 0.0 ? 0.3 v v oh output high level (driven) notes 4 , 6 2.8 ? 3.6 v v se1 single-ended one 0.8 ? ? v v crs output signal crossover voltage note 10 1.3 ? 2.0 v c io i/o capacitance pin/ball to ground ? ? 20 pf table 11-25. usb high-s peed dc specifications symbol parameter conditions min typ max unit v hssq high-speed squelch detection threshold (differential signal amplitude) 100 ? 150 mv v hsdsc high-speed disconnect detection threshold (differential signal amplitude) 525 ? 625 mv ? high-speed differential input signaling levels specified by eye patterns ? ? ? ? v hscm high-speed data signaling common mode voltage range -50 ? +500 mv v hsoi high-speed idle level -10 ? +10 mv v hsoh high-speed data signaling high 360 ? 440 mv v hsol high-speed data signaling low -10 ? +10 mv v chirpj chirp j level (differential voltage) 700 ? 1100 mv v chirpk chirp k level (differential voltage) -900 ? -500 mv c io i/o capacitance pin/ball to ground ? ? 20 pf
electrical specifications plx technology, inc. 108 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.3.5 local bus dc specifications operating conditions ? vddc = 2.2 to 2.6v, vddio = 1.7 to 3.5v, t a = 0 to 85c typical values ? vddc = 2.5v, vddio = 3.3v, t a = 25c table 11-26. local bus dc specifications symbol parameter conditions min typ max unit v ih 5.0v tolerant input high voltage 2.0 ? 5.5 v v il 5.0v tolerant input low voltage 0 ? 0 v i il input leakage 0v < v in < 5.5v -10 ? +10 a i oz hi-z state data line leakage 0v < v in < 5.5v ? ? 10 a v oh 5.0v tolerant input high voltage i out = -12 ma 2.4 ? ? v v ol 5.0v tolerant input low voltage i out = +12 ma ? ? 0.4 v c in input capacitance pin/ball to ground ? ? 10 pf c clk clk pin/ball capacitance pin/ball to ground 5 ? 12 pf c idsel idsel pin/ball capacitance pin/ball to ground ? ? 8 pf
august, 2005 ac specifications net2272 local bus to usb 2.0 peripheral controller data book 109 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4 ac specifications 11.4.1 usb full- and high-speed port ac specifications operating conditions ? vddc = 2.2 to 2.6v, vddio = 1.7 to 3.5v, t a = 0 to 85c typical values ? vddc = 2.5v, vddio = 3.3v, t a = 25c table 11-27. usb full-speed port ac specifications symbol parameter conditions waveform min typ max unit t fr full-speed rise time c l = 50 pf, note 10 figure 11-2 4 ? 20 ns t ff full-speed fall time figure 11-1 4 ? 20 ns t frfm rise and fall time matching (t fr / t ff ), note 10 figure 11-1 figure 11-2 90 ? 110 % z drv driver output resistance stea dy state drive ? 10 ? 15 ohms t fdraths full-speed data rate ? 11.994 12 12.006 mbps t dj1 source differential driver jitter to next transition notes 7 , 8 , 10 , 12 figure 11-3 -2 0 2 ns t dj2 source differential driver jitter for paired transitions notes 7 , 8 , 10 , 12 figure 11-3 -1 0 +1 ns t fdeop source jitter for differential transition to se0 transition notes 8 , 11 figure 11-4 -2 0 +5 ns t jr1 receiver data jitter tolerance to next transition note 8 figure 11-5 -18.5 0 +18.5 ns t jr2 receiver data jitter tolerance for paired transitions note 8 figure 11-5 -9 0 +9 ns t feopt source se0 interval of eop figure 11-4 160 167 175 ns t feopr receiver se0 interval of eop note 13 figure 11-4 82 ? ? ns t fst width of se0 interval during differential transition ? 14 ? ? ns table 11-28. usb high-speed port ac specifications symbol parameter conditions waveform min typ max unit t hsr high-speed rise time note 16 ? 500 ? ? ps t hsf high-speed fall time ? 500 ? ? ps z drv driver output resistance steady state drive ? 10 ? 15 ohms t hsdrv high-speed data rate ? 479.760 480 480.240 mbps ? data source jitter note 17 ? ? ? ? ? ? receiver jitter tolerance note 17 ? ? ? ? ?
electrical specifications plx technology, inc. 110 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.2 usb full-speed port ac waveforms figure 11-1. data signal rise and fall time figure 11-2. full-speed load figure 11-3. source differential driver jitter t ff t fr
august, 2005 usb full-speed port ac waveforms net2272 local bus to usb 2.0 peripheral controller data book 111 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 figure 11-4. differential to eop transition skew and eop width figure 11-5. receiver jitter tolerance
electrical specifications plx technology, inc. 112 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.3 usb port ac/dc specification notes 1. measured at a plug. 2. measured at a receptacle. 3. measured at b receptacle. 4. measured at a or b connector. 5. measured with rl of 1.425k ohms to 3.6v. 6. measured with rl of 14.25k ohms to ground. 7. timing difference between the differential data signals. 8. measured at crossover point of differential data signals. 9. the maximum load specification is the maximum effective capacitive load allowed that meets the target hub vbus drop of 330 mv. 10. excluding the first transition from the idle state. 11. the two transitions should be a (nominal) bit time apart. 12. for both transitions of differential signaling. 13. must accept as valid eop. 14. single-ended capacitance of d+ or d- is the capacitance of d+/d- to all other conductors and, if present, shield in the cable. that is , to measure the single-ended capacitance of d+, short d-, vbus, ground, and the shield line together and measure the capacitance of d+ to the other conductors. 15. for high-power devices (non-hubs) when enabled for device-remote wakeup. 16. measured from 10 to 90 pe rcent of the data signal. 17. source and receiver jitter specified by the eye pattern templates in the usb r2.0 , section 7.1.2.2.
august, 2005 1.8v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 113 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.4 1.8v vddio loca l bus ac specifications 11.4.4.1 1.8v vddio local bu s non-multiplexed write operating conditions ? vddc = 2.2 to 2.6v, vddio = 1.7 to 1.9v, t a = 0 to 85c, output load = 25 pf notes: 1. write enable is the occurren ce of both cs# and iow#. 2. because reading and writing to ep_data cause ep_availx and ep_transferx to change values, it is necessary to increase the recove ry time to 70 ns between a read or write to ep_data and a read from ep_availx or ep_transferx . table 11-29. 1.8v vddio local bus non-multiplexed write specifications symbol parameter min max unit notes t10 address setup to end of write enable 5 ns 1 t11 address hold from end of write enable 0 ns 1 t12 write enable width 5 ns 1 t13 data setup to end of write enable 5 ns 1 t14 data hold time from end of write enable 0 ns 1 t15a recovery time to next write 28 ns t15b recovery time to next read 52 ns 2 t11 t11 t12 t10 t13 t15a t12 t10 t13 t14 t14 a0 a1 d0 d1 0ns 10ns 20ns 30ns 40ns 50ns 60ns la[4:0] cs# and iow# ld[15:0]
electrical specifications plx technology, inc. 114 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.4.2 1.8v vddio local bus multiplexed write operating conditions ? vddc = 2.2 to 2.6v, vddio = 1.7 to 1.9v, t a = 0 to 85c, output load = 25 pf notes: 1. write enable is the occurren ce of both cs# and iow#. 2. because reading and writing to ep_data cause ep_availx and ep_transferx to change values, it is necessary to increase the recove ry time to 70 ns between a read or write to ep_data and a read from ep_availx or ep_transferx . table 11-30. 1.8v vddio local bus multiplexed write specifications symbol parameter min max unit notes t1 address setup to falling edge of ale 5 ns t2 address hold from falling edge of ale 1 ns t3 ale width 5 ns t12 write enable width 5 ns 1 t13 data setup to end of write enable 5 ns 1 t14 data hold time from end of write enable 0 ns 1 t15a recovery time to next write 28 ns t15b recovery time to next read 52 ns 2 t19 ale falling edge to write enable 1 ns 1 t1 t3 t1 t3 t19 t12 t13 t15a t19 t12 t13 t2 t14 t2 t14 d0 d1 a0 a1 0ns 10ns 20ns 30ns 40ns 50ns 60ns ale cs# and iow# ld[15:0]
august, 2005 1.8v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 115 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.4.3 1.8v vddio local bus non-multiplexed read operating conditions ? vddc = 2.2 to 2.6v, vddio = 1.7 to 1.9v, t a = 0 to 85c, output load = 25 pf notes: 1. read enable is the occurren ce of both cs# and ior#. 2. because reading and writing to ep_data cause ep_availx and ep_transferx to change values, it is necessary to increase the recove ry time to 37 ns between a read or write to ep_data and a read from ep_availx or ep_transferx . table 11-31. 1.8v vddio local bus non-multiplexed read specifications symbol parameter min max unit notes t4 address setup to read enable -1 ns 1 t5 address hold from end of read enable -2 ns 1 t6 data access time from la valid or read enable asserted, whichever is later 30 ns 1 t7 data three-state time from end of read enable 3 16 ns 1 t8a recovery time to next read 24 ns 2 t8b recovery time to next write 24 ns t16 read cycle time 54 ns t5 t5 t4 t4 t8a t16 t6 t7 t6 t7 a0 a1 d0 d1 0ns 25ns 50ns 75ns 100ns la[4:0] cs# and ior# ld[15:0]
electrical specifications plx technology, inc. 116 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.4.4 1.8v vddio local bus multiplexed read operating conditions ? vddc = 2.2 to 2.6v, vddio = 1.7 to 1.9v, t a = 0 to 85c, output load = 25 pf notes: 1. read enable is the occurren ce of both cs# and ior#. 2. because reading and writing to ep_data cause ep_availx and ep_transferx to change values, it is necessary to increase the recove ry time to 37 ns between a read or write to ep_data and a read from ep_availx or ep_transferx . table 11-32. 1.8v vddio local bus multiplexed read specifications symbol parameter min max unit notes t1 address setup to falling edge of ale 5 ns t2 address hold from falling edge of ale 1 ns t3 ale width 5 ns t6 data access time from read enable 30 ns 1 t7 data three-state time from end of read enable 3 15 ns 1 t8a recovery time to next read 24 ns 2 t8b recovery time to next write 24 ns t9 recovery time to next ale 5 ns t16 read cycle time 54 ns t19 ale falling edge to read enable 1 ns 1 t3 t1 t9 t3 t1 t19 t8a t16 t19 t2 t6 t7 t2 t6 t7 d0 d1 a0 a1 0ns 25ns 50ns 75ns ale cs# and ior# ld[15:0]
august, 2005 1.8v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 117 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.4.5 1.8v vddio local bu s dma write ? slow mode operating conditions ? vddc = 2.2 to 2.6v, vddio = 1.7 to 1.9v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split mode, write enable is the occurrence of dack# and optionally, iow#. for dma split mode, write enable is the occurrence of dack# and optionally, dmawr#. 2. the minimum value is gu aranteed only if the dmareq register dma request enable bit is set. 3. eot#, dack#, and optionally, iow# or dmawr#, must all be true for at least t29 for proper recognition of the eot# pulse. table 11-33. 1.8v vddio local bus dma write ? slow mode specifications symbol parameter min typ max unit notes t20 write enable true to dreq false 44 59 70 ns 2 t21 write enable false to dreq true 26 43 54 ns t25 dreq false to dreq true 14 34 ns t26 write enable width 40 ns 1 t27 data setup to end of write enable 10 ns 1 t28 data hold time from end of write enable 0 ns 1 t29 width of eot# pulse 40 ns 3 t20 t25 t21 t20 t27 t26 t27 t26 t28 t28 t29 d0 d1 0ns 50ns 100ns 150ns 200ns dreq dack# iow# (optional) ld[15:0] eot# (optional)
electrical specifications plx technology, inc. 118 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.4.6 1.8v vddio local bu s dma write ? fast mode operating conditions ? vddc = 2.2 to 2.6v, vddio = 1.7 to 1.9v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split mode, write enable is the occurrence of dack# and optionally, iow#. for dma split mode, write enable is the occurrence of dack# and optionally, dmawr#. 2. the minimum value is gu aranteed only if the dmareq register dma request enable bit is set. 3. eot#, dack#, and optionally, iow# or dmawr#, must all be true for at least t29 for proper recognition of the eot# pulse. table 11-34. 1.8v vddio local bus dma write ? fast mode specifications symbol parameter min typ max unit notes t20 write enable true to dreq false 8 33 ns 2 t21 write enable false to dreq true 25 39 55 ns t25 dreq false to dreq true 52 60 ns t26 write enable width 40 ns 1 t27 data setup to end of write enable 10 ns 1 t28 data hold time from end of write enable 0 ns 1 t29 width of eot# pulse 40 ns 3 t20 t25 t21 t20 t27 t26 t27 t26 t28 t28 t29 d0 d1 0ns 50ns 100ns 150ns 200ns dreq dack# iow# (optional) ld[15:0] eot# (optional)
august, 2005 1.8v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 119 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.4.7 1.8v vddio local bu s dma write ? burst mode operating conditions ? vddc = 2.2 to 2.6v, vddio = 1.7 to 1.9v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split mode, write enable is the occurrence of dack# and optionally, iow#. for dma split mode, write enable is the occurrence of dack# and optionally, dmawr#. 3. eot#, dack#, and optionally, iow# or dmawr#, must all be true for at least t29 for proper recognition of the eot# pulse. table 11-35. 1.8v vddio local bus dma write ? burst mode specifications symbol parameter min typ max unit notes t20 write enable true to dreq false 8 33 ns t26 write enable width 38 ns 1 t27 data setup to end of write enable 10 ns 1 t28 data hold time from end of write enable 0 ns 1 t29 width of eot# pulse 40 ns 3 t30 dma write recovery 28 ns t20 t27 t26 t30 t26 t27 t30 t27 t26 t28 t28 t28 t29 d0 d2 d1 0ns 25ns 50ns 75ns 100ns 125ns dreq dack# iow# (optional) ld[15:0] eot# (optional)
electrical specifications plx technology, inc. 120 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.4.8 1.8v vddio local bu s dma read ? slow mode operating conditions ? vddc = 2.2 to 2.6v, vddio = 1.7 to 1.9v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split mode, read enable is the occurrence of dack# and optionally, ior#. for dma split mode, read enable is the occurrence of dack# and optionally, dmard#. 2. the minimum value is gu aranteed only if the dmareq register dma request enable bit is set. 3. eot#, dack#, and optionally, ior# or dmard#, must all be true for at least t24 for proper recognition of the eot# pulse. 4. a recovery time of 2 ns is required between dma read enable de-assertion and i/o read enable assertion. (this note is a general requirement not shown on the timing diagrams.) table 11-36. 1.8v vddio local bus dma read ? slow mode specifications symbol parameter min typ max unit notes t20 read enable true to dreq false 28 47 67 ns 2 t21 read enable false to dreq true 40 55 66 ns t22 data access time from read enable 25 ns 1 t23 data three-state time from end of read enable 2 16 ns 1 t24 width of eot# pulse 40 ns 3 t25 dreq false to dreq true 23 33 ns t20 t21 t25 t20 t22 t23 t22 t23 t24 d0 d1 0ns 50ns 100ns 150ns 200ns dreq dack# ior# (optional) ld[15:0] eot# (optional)
august, 2005 1.8v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 121 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.4.9 1.8v vddio local bu s dma read ? fast mode operating conditions ? vddc = 2.2 to 2.6v, vddio = 1.7 to 1.9v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split mode, read enable is the occurrence of dack# and optionally, ior#. for dma split mode, read enable is the occurrence of dack# and optionally, dmard#. 2. the minimum value is only guaranteed if the dmareq register dma request enable bit is set. 3. eot#, dack#, and optionally, ior# or dmard#, must all be true for at least t24 for proper recognition of the eot# pulse. 4. a recovery time of 2 ns is required between dma read enable de-assertion and i/o read enable assertion. (this note is a general requirement not shown on the timing diagrams.) table 11-37. 1.8v vddio local bus dma read ? fast mode specifications symbol parameter min typ max unit notes t20 read enable true to dreq false 8 30 ns 2 t21 read enable false to dreq true 7 15 25 ns t22 data access time from read enable 25 ns 1 t23 data three-state time from end of read enable 3 16 ns 1 t24 width of eot# pulse 40 ns 3 t25 dreq false to dreq true 33 36 ns t20 t21 t25 t20 t22 t23 t22 t23 t24 d0 d1 0ns 50ns 100ns 150ns 200ns dreq dack# ior# (optional) ld[15:0] eot# (optional)
electrical specifications plx technology, inc. 122 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.4.10 1.8v vddio local bus dma read ? burst mode operating conditions ? vddc = 2.2 to 2.6v, vddio = 1.7 to 1.9v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split mode, read enable is the occurrence of dack# and optionally, ior#. for dma split mode, read enable is the occurrence of dack# and optionally, dmard#. 3. eot#, dack#, and optionally, ior# or dmard#, must all be true for at least t24 for proper recognition of the eot# pulse. 4. a recovery time of 2 ns is required between dma read enable de-assertion and i/o read enable assertion. (this note is a general requirement not shown on the timing diagrams.) table 11-38. 1.8v vddio local bus dma read ? burst mode specifications symbol parameter min typ max unit notes t17 dma read cycle time 44 ns t18 dma read recovery time 19 ns t20 read enable true to dreq false 8 31 ns t22 data access time from read enable 25 ns 1 t23 data three-state time from end of read enable 5 16 ns 1 t24 width of eot# pulse 40 ns 3 t20 t18 t17 t18 t17 t22 t23 t22 t23 t22 t23 t24 d0 d2 d1 0ns 25ns 50ns 75ns 100ns 125ns 150ns dreq dack# ior# (optional) ld[15:0] eot# (optional)
august, 2005 2.5v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 123 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.5 2.5v vddio loca l bus ac specifications 11.4.5.1 2.5v vddio local bu s non-multiplexed write operating conditions ? vddc and vddio = 2.2 to 2.6v, t a = 0 to 85c, output load = 25 pf notes: 1. write enable is the occurren ce of both cs# and iow#. 2. because reading and writing to ep_data cause ep_availx and ep_transferx to change values, it is necessary to increase the recove ry time to 70 ns between a read or write to ep_data and a read from ep_availx or ep_transferx . table 11-39. 2.5v vddio local bus non-multiplexed write specifications symbol parameter min max unit notes t10 address setup to end of write enable 5 ? ns 1 t11 address hold from end of write enable 0 ? ns 1 t12 write enable width 5 ? ns 1 t13 data setup to end of write enable 5 ? ns 1 t14 data hold time from end of write enable 0 ? ns 1 t15a recovery time to next write 28 ? ns t15b recovery time to next read 52 ? ns 2 t11 t11 t12 t10 t13 t15a t12 t10 t13 t14 t14 a0 a1 d0 d1 0ns 10ns 20ns 30ns 40ns 50ns 60ns la[4:0] cs# and iow# ld[15:0]
electrical specifications plx technology, inc. 124 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.5.2 2.5v vddio local bus multiplexed write operating conditions ? vddc and vddio = 2.2 to 2.6v, t a = 0 to 85c, output load = 25 pf notes: 1. write enable is the occurren ce of both cs# and iow#. 2. because reading and writing to ep_data cause ep_availx and ep_transferx to change values, it is necessary to increase the recove ry time to 70 ns between a read or write to ep_data and a read from ep_availx or ep_transferx . table 11-40. 2.5v vddio local bus multiplexed write specifications symbol parameter min max unit notes t1 address setup to falling edge of ale 5 ? ns t2 address hold from falling edge of ale 1 ? ns t3 ale width 5 ? ns t12 write enable width 5 ? ns 1 t13 data setup to end of write enable 5 ? ns 1 t14 data hold time from end of write enable 0 ? ns 1 t15a recovery time to next write 28 ? ns t15b recovery time to next read 52 ? ns 2 t19 ale falling edge to write enable 1 ? ns 1 t1 t3 t1 t3 t19 t12 t13 t15a t19 t12 t13 t2 t14 t2 t14 d0 d1 a0 a1 0ns 10ns 20ns 30ns 40ns 50ns 60ns ale cs# and iow# ld[15:0]
august, 2005 2.5v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 125 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.5.3 2.5v vddio local bus non-multiplexed read operating conditions ? vddc and vddio = 2.2 to 2.6v, t a = 0 to 85c, output load = 25 pf notes: 1. read enable is the occurren ce of both cs# and ior#. 2. because reading and writing to ep_data cause ep_availx and ep_transferx to change values, it is necessary to increase the recove ry time to 37 ns between a read or write to ep_data and a read from ep_availx or ep_transferx . table 11-41. 2.5v vddio local bus non-multiplexed read specifications symbol parameter min max unit notes t4 address setup to read enable -1 ? ns 1 t5 address hold from end of read enable -2 ? ns 1 t6 data access time from la valid or read enable asserted (whichever occurs later) ? 23 ns 1 t7 data three-state time from end of read enable 2 11 ns 1 t8a recovery time to next read 19 ? ns 2 t8b recovery time to next write 19 ? ns t16 read cycle time 42 ? ns t5 t5 t4 t4 t8a t16 t6 t7 t6 t7 a0 a1 d0 d1 0ns 25ns 50ns 75ns 100ns la[4:0] cs# and ior# ld[15:0]
electrical specifications plx technology, inc. 126 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.5.4 2.5v vddio local bus multiplexed read operating conditions ? vddc and vddio = 2.2 to 2.6v, t a = 0 to 85c, output load = 25 pf notes: 1. read enable is the occurren ce of both cs# and ior#. 2. because reading and writing to ep_data cause ep_availx and ep_transferx to change values, it is necessary to increase the recove ry time to 37 ns between a read or write to ep_data and a read from ep_availx or ep_transferx . table 11-42. 2.5v vddio local bus multiplexed read specifications symbol parameter min max unit notes t1 address setup to falling edge of ale 5 ? ns t2 address hold from falling edge of ale 1 ? ns t3 ale width 5 ? ns t6 data access time from read enable ? 23 ns 1 t7 data three-state time from end of read enable 2 11 ns 1 t8a recovery time to next read 19 ? ns 2 t8b recovery time to next write 19 ? ns t9 recovery time to next ale 5 ? ns t16 read cycle time 42 ? ns t19 ale falling edge to read enable 1 ? ns 1 t3 t1 t9 t3 t1 t19 t8a t16 t19 t2 t6 t7 t2 t6 t7 d0 d1 a0 a1 0ns 25ns 50ns 75ns ale cs# and ior# ld[15:0]
august, 2005 2.5v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 127 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.5.5 2.5v vddio local bu s dma write ? slow mode operating conditions ? vddc and vddio = 2.2 to 2.6v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split bus mode, write enable is the occurrence of dack# and optionally, iow#. for dma split bus mode, write enable is the occurrence of dack# and optionally, dmawr#. 2. minimum value is guaranteed only if the dmareq register dma request enable bit is set. 3. eot#, dack#, and optionally, iow# or dmawr#, must all be true for at least t29 for proper recognition of the eot# pulse. table 11-43. 2.5v vddio local bus dma write ? slow mode specifications symbol parameter min typ max unit notes t20 write enable true to dreq false 17 50 60 ns 2 t21 write enable false to dreq true 23 58 75 ns t25 dreq false to dreq true 15 25 ? ns t26 write enable width 5 ? ? ns 1 t27 data setup to end of write enable 5 ? ? ns 1 t28 data hold time from end of write enable 0 ? ? ns 1 t29 eot# pulse width 5 ? ? ns 3 t31 dreq true to write enable true 9 ? ? ns 1 t20 t25 t21 t20 t31 t27 t26 t31 t27 t26 t28 t28 t29 d0 d1 0ns 50ns 100ns 150ns 200ns dreq dack# iow# (optional) ld[15:0] eot# (optional)
electrical specifications plx technology, inc. 128 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.5.6 2.5v vddio local bu s dma write ? fast mode operating conditions ? vddc and vddio = 2.2 to 2.6v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split bus mode, write enable is the occurrence of dack# and optionally, iow#. for dma split bus mode, write enable is the occurrence of dack# and optionally, dmawr#. 2. minimum value is guaranteed only if the dmareq register dma request enable bit is set. 3. eot#, dack#, and optionally, iow# or dmawr#, must all be true for at least t29 for proper recognition of the eot# pulse. table 11-44. 2.5v vddio local bus dma write ? fast mode specifications symbol parameter min typ max unit notes t20 write enable true to dreq false 4 ? 23 ns 2 t21 write enable false to dreq true 16 45 55 ns t25 dreq false to dreq true 15 40 ? ns t26 write enable width 5 ? ? ns 1 t27 data setup to end of write enable 5 ? ? ns 1 t28 data hold time from end of write enable 0 ? ? ns 1 t29 eot# pulse width 5 ? ? ns 3 t20 t25 t21 t20 t27 t26 t27 t26 t28 t28 t29 d0 d1 0ns 50ns 100ns 150ns 200ns dreq dack# iow# (optional) ld[15:0] eot# (optional)
august, 2005 2.5v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 129 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.5.7 2.5v vddio local bu s dma write ? burst mode operating conditions ? vddc and vddio = 2.2 to 2.6v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split bus mode, write enable is the occurrence of dack# and optionally, iow#. for dma split bus mode, write enable is the occurrence of dack# and optionally, dmawr#. 3. eot#, dack#, and optionally, iow# or dmawr#, must all be true for at least t29 for proper recognition of the eot# pulse. table 11-45. 2.5v vddio local bus dma write ? burst mode specifications symbol parameter min typ max unit notes t20 write enable true to dreq false 4 ? 23 ns t26 write enable width 5 ? ? ns 1 t27 data setup to end of write enable 5 ? ? ns 1 t28 data hold time from end of write enable 0 ? ? ns 1 t29 eot# pulse width 5 ? ? ns 3 t30 dma write recovery 36 ? ? ns t20 t27 t26 t30 t26 t27 t30 t27 t26 t28 t28 t28 t29 d0 d2 d1 0ns 25ns 50ns 75ns 100ns 125ns dreq dack# iow# (optional) ld[15:0] eot# (optional)
electrical specifications plx technology, inc. 130 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.5.8 2.5v vddio local bu s dma read ? slow mode operating conditions ? vddc and vddio = 2.2 to 2.6v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split bus mode, read enable is the occurrence of dack# and optionally, ior#. for dma split bus mode, read enable is the occurrence of dack# and optionally, dmard#. 2. minimum value is guaranteed only if the dmareq register dma request enable bit is set. 3. eot#, dack#, and optionally, ior# or dmard#, must all be true for at least t24 for proper recognition of the eot# pulse. 4. a recovery time of 2 ns is required between dma read enable de-assertion and i/o read enable assertion. (this note is a general requirement not shown on the timing diagrams.) table 11-46. 2.5v vddio local bus dma read ? slow mode specifications symbol parameter min typ max unit notes t20 read enable true to dreq false 25 50 60 ns 2 t21 read enable false to dreq true 16 50 68 ns t22 data access time from read enable ? ? 17 ns 1 t23 data three-state time from end of read enable 2 ? 12 ns 1 t24 eot# pulse width 10 ? ? ns 3 t25 dreq false to dreq true 15 25 ? ns t20 t21 t25 t20 t22 t23 t22 t23 t24 d0 d1 0ns 50ns 100ns 150ns 200ns dreq dack# ior# (optional) ld[15:0] eot# (optional)
august, 2005 2.5v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 131 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.5.9 2.5v vddio local bu s dma read ? fast mode operating conditions ? vddc and vddio = 2.2 to 2.6v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split bus mode, read enable is the occurrence of dack# and optionally, ior#. for dma split bus mode, read enable is the occurrence of dack# and optionally, dmard#. 2. minimum value is guaranteed only if the dmareq register dma request enable bit is set. 3. eot#, dack#, and optionally, ior# or dmard#, must all be true for at least t24 for proper recognition of the eot# pulse. 4. a recovery time of 2 ns is required between dma read enable de-assertion and i/o read enable assertion. (this note is a general requirement not shown on the timing diagrams.) table 11-47. 2.5v vddio local bus dma read ? fast mode specifications symbol parameter min typ max unit notes t20 read enable true to dreq false 4 ? 21 ns 2 t21 read enable false to dreq true 4 35 45 ns t22 data access time from read enable ? ? 17 ns 1 t23 data three-state time from end of read enable 2 ? 12 ns 1 t24 eot# pulse width 10 ? ? ns 3 t25 dreq false to dreq true 15 36 ? ns t20 t21 t25 t20 t22 t23 t22 t23 t24 d0 d1 0ns 50ns 100ns 150ns 200ns dreq dack# ior# (optional) ld[15:0] eot# (optional)
electrical specifications plx technology, inc. 132 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.5.10 2.5v vddio local bus dma read ? burst mode operating conditions ? vddc and vddio = 2.2 to 2.6v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split bus mode, read enable is the occurrence of dack# and optionally, ior#. for dma split bus mode, read enable is the occurrence of dack# and optionally, dmard#. 3. eot#, dack#, and optionally, ior# or dmard#, must all be true for at least t24 for proper recognition of the eot# pulse. 4. a recovery time of 2 ns is required between dma read enable de-assertion and i/o read enable assertion. (this note is a general requirement not shown on the timing diagrams.) table 11-48. 2.5v vddio local bus dma read ? burst mode specifications symbol parameter min typ max unit notes t17 dma read cycle time 36 ? ? ns t18 dma read recovery time 19 ? ? ns t20 read enable true to dreq false 4 ? 22 ns t22 data access time from read enable ? ? 17 ns 1 t23 data three-state time from end of read enable 2 ? 12 ns 1 t24 eot# pulse width 10 ? ? ns 3 t20 t18 t17 t18 t17 t22 t23 t22 t23 t22 t23 t24 d0 d2 d1 0ns 25ns 50ns 75ns 100ns 125ns 150ns dreq dack# ior# (optional) ld[15:0] eot# (optional)
august, 2005 3.3v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 133 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.6 3.3v vddio loca l bus ac specifications 11.4.6.1 3.3v vddio local bu s non-multiplexed write operating conditions ? vddc = 2.2 to 2.6v, vddio = 3.2 to 3.5v, t a = 0 to 85c, output load = 25 pf notes: 1. write enable is the occurren ce of both cs# and iow#. 2. because reading and writing to ep_data cause ep_avail x and ep_transfer x to change values, it is necessary to increase the recovery time to 70 ns between a read or write to ep_data and a read from ep_avail x or ep_transfer x . table 11-49. 3.3v vddio local bus non-multiplexed write specifications symbol parameter min max unit notes t10 address setup to end of write enable 5 ? ns 1 t11 address hold from end of write enable 0 ? ns 1 t12 write enable width 5 ? ns 1 t13 data setup to end of write enable 5 ? ns 1 t14 data hold time from end of write enable 0 ? ns 1 t15a recovery time to next write 28 ? ns t15b recovery time to next read 52 ? ns 2 t11 t11 t12 t10 t13 t15a t12 t10 t13 t14 t14 a0 a1 d0 d1 0ns 10ns 20ns 30ns 40ns 50ns 60ns la[4:0] cs# and iow# ld[15:0]
electrical specifications plx technology, inc. 134 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.6.2 3.3v vddio local bus multiplexed write operating conditions ? vddc = 2.2 to 2.6v, vddio = 3.2 to 3.5v, t a = 0 to 85c, output load = 25 pf notes: 1. write enable is the occurren ce of both cs# and iow#. 2. because reading and writing to ep_data cause ep_availx and ep_transferx to change values, it is necessary to increase the recove ry time to 70 ns between a read or write to ep_data and a read from ep_availx or ep_transferx . table 11-50. 3.3v vddio local bus multiplexed write specifications symbol parameter min max unit notes t1 address setup to falling edge of ale 5 ? ns t2 address hold from falling edge of ale 1 ? ns t3 ale width 5 ? ns t12 write enable width 5 ? ns 1 t13 data setup to end of write enable 5 ? ns 1 t14 data hold time from end of write enable 0 ? ns 1 t15a recovery time to next write 28 ? ns t15b recovery time to next read 52 ? ns 2 t19 ale falling edge to write enable 1 ? ns 1 t1 t3 t1 t3 t19 t12 t13 t15a t19 t12 t13 t2 t14 t2 t14 d0 d1 a0 a1 0ns 10ns 20ns 30ns 40ns 50ns 60ns ale cs# and iow# ld[15:0]
august, 2005 3.3v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 135 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.6.3 3.3v vddio local bus non-multiplexed read operating conditions ? vddc = 2.2 to 2.6v, vddio = 3.2 to 3.5v, t a = 0 to 85c, output load = 25 pf notes: 1. read enable is the occurren ce of both cs# and ior#. 2. because reading and writing to ep_data cause ep_availx and ep_transferx to change values, it is necessary to increase the recove ry time to 37 ns between a read or write to ep_data and a read from ep_availx or ep_transferx . table 11-51. 3.3v vddio local bus non-multiplexed read specifications symbol parameter min max unit notes t4 address setup to read enable -1 ? ns 1 t5 address hold from end of read enable -2 ? ns 1 t6 data access time from la valid or read enable asserted (whichever occurs later) ? 18 ns 1 t7 data three-state time from end of read enable 2 11 ns 1 t8a recovery time to next read 19 ? ns 2 t8b recovery time to next write 19 ? ns t16 read cycle time 37 ? ns t5 t5 t4 t4 t8a t16 t6 t7 t6 t7 a0 a1 d0 d1 0ns 25ns 50ns 75ns 100ns la[4:0] cs# and ior# ld[15:0]
electrical specifications plx technology, inc. 136 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.6.4 3.3v vddio local bus multiplexed read operating conditions ? vddc = 2.2 to 2.6v, vddio = 3.2 to 3.5v, t a = 0 to 85c, output load = 25 pf notes: 1. read enable is the occurren ce of both cs# and ior#. 2. because reading and writing to ep_data cause ep_availx and ep_transferx to change values, it is necessary to increase the recove ry time to 37 ns between a read or write to ep_data and a read from ep_availx or ep_transferx . table 11-52. 3.3v vddio local bus multiplexed read specifications symbol parameter min max unit notes t1 address setup to falling edge of ale 5 ? ns t2 address hold from falling edge of ale 1 ? ns t3 ale width 5 ? ns t6 data access time from read enable ? 18 ns 1 t7 data three-state time from end of read enable 2 11 ns 1 t8a recovery time to next read 19 ? ns 2 t8b recovery time to next write 19 ? ns t9 recovery time to next ale 5 ? ns t16 read cycle time 37 ? ns t19 ale falling edge to read enable 1 ? ns 1 t3 t1 t9 t3 t1 t19 t8a t16 t19 t2 t6 t7 t2 t6 t7 d0 d1 a0 a1 0ns 25ns 50ns 75ns ale cs# and ior# ld[15:0]
august, 2005 3.3v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 137 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.6.5 3.3v vddio local bu s dma write ? slow mode operating conditions ? vddc = 2.2 to 2.6v, vddio = 3.2 to 3.5v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split bus mode, write enable is the occurrence of dack# and optionally, iow#. for dma split bus mode, write enable is the occurrence of dack# and optionally, dmawr#. 2. minimum value is guaranteed only if the dmareq register dma request enable bit is set. 3. eot#, dack#, and optionally, iow# or dmawr#, must all be true for at least t29 for proper recognition of the eot# pulse. table 11-53. 3.3v vddio local bus dma write ? slow mode specifications symbol parameter min typ max unit notes t20 write enable true to dreq false 17 50 60 ns 2 t21 write enable false to dreq true 23 50 72 ns t25 dreq false to dreq true 15 25 ? ns t26 write enable width 5 ? ? ns 1 t27 data setup to end of write enable 5 ? ? ns 1 t28 data hold time from end of write enable 0 ? ? ns 1 t29 eot# pulse width 5 ? ? ns 3 t31 dreq true to write enable true 9 ? ? ns 1 t20 t25 t21 t20 t31 t27 t26 t31 t27 t26 t28 t28 t29 d0 d1 0ns 50ns 100ns 150ns 200ns dreq dack# iow# (optional) ld[15:0] eot# (optional)
electrical specifications plx technology, inc. 138 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.6.6 3.3v vddio local bu s dma write ? fast mode operating conditions ? vddc = 2.2 to 2.6v, vddio = 3.2 to 3.5v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split bus mode, write enable is the occurrence of dack# and optionally, iow#. for dma split bus mode, write enable is the occurrence of dack# and optionally, dmawr#. 2. minimum value is guaranteed only if the dmareq register dma request enable bit is set. 3. eot#, dack#, and optionally, iow# or dmawr#, must all be true for at least t29 for proper recognition of the eot# pulse. table 11-54. 3.3v vddio local bus dma write ? fast mode specifications symbol parameter min typ max unit notes t20 write enable true to dreq false 4 ? 19 ns 2 t21 write enable false to dreq true 16 45 55 ns t25 dreq false to dreq true 15 40 ? ns t26 write enable width 5 ? ? ns 1 t27 data setup to end of write enable 5 ? ? ns 1 t28 data hold time from end of write enable 0 ? ? ns 1 t29 eot# pulse width 5 ? ? ns 3 t20 t25 t21 t20 t27 t26 t27 t26 t28 t28 t29 d0 d1 0ns 50ns 100ns 150ns 200ns dreq dack# iow# (optional) ld[15:0] eot# (optional)
august, 2005 3.3v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 139 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.6.7 3.3v vddio local bu s dma write ? burst mode operating conditions ? vddc = 2.2 to 2.6v, vddio = 3.2 to 3.5v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split bus mode, write enable is the occurrence of dack# and optionally, iow#. for dma split bus mode, write enable is the occurrence of dack# and optionally, dmawr#. 3. eot#, dack#, and optionally, iow# or dmawr#, must all be true for at least t29 for proper recognition of the eot# pulse. table 11-55. 3.3v vddio local bus dma write ? burst mode specifications symbol parameter min typ max unit notes t20 write enable true to dreq false 4 ? 20 ns t26 write enable width 5 ? ? ns 1 t27 data setup to end of write enable 5 ? ? ns 1 t28 data hold time from end of write enable 0 ? ? ns 1 t29 eot# pulse width 5 ? ? ns 3 t30 dma write recovery 36 ? ? ns t20 t27 t26 t30 t26 t27 t30 t27 t26 t28 t28 t28 t29 d0 d2 d1 0ns 25ns 50ns 75ns 100ns 125ns dreq dack# iow# (optional) ld[15:0] eot# (optional)
electrical specifications plx technology, inc. 140 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.6.8 3.3v vddio local bu s dma read ? slow mode operating conditions ? vddc = 2.2 to 2.6v, vddio = 3.2 to 3.5v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split bus mode, read enable is the occurrence of dack# and optionally, ior#. for dma split bus mode, read enable is the occurrence of dack# and optionally, dmard#. 2. minimum value is guaranteed only if the dmareq register dma request enable bit is set. 3. eot#, dack#, and optionally, ior# or dmard#, must all be true for at least t24 for proper recognition of the eot# pulse. 4. a recovery time of 2 ns is required between dma read enable de-assertion and i/o read enable assertion. (this note is a general requirement not shown on the timing diagrams.) table 11-56. 3.3v vddio local bus dma read ? slow mode specifications symbol parameter min typ max unit notes t20 read enable true to dreq false 25 50 60 ns 2 t21 read enable false to dreq true 16 50 68 ns t22 data access time from read enable ? ? 16 ns 1 t23 data three-state time from end of read enable 2 ? 12 ns 1 t24 eot# pulse width 10 ? ? ns 3 t25 dreq false to dreq true 15 25 ? ns t20 t21 t25 t20 t22 t23 t22 t23 t24 d0 d1 0ns 50ns 100ns 150ns 200ns dreq dack# ior# (optional) ld[15:0] eot# (optional)
august, 2005 3.3v vddio local bus ac specifications net2272 local bus to usb 2.0 peripheral controller data book 141 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.6.9 3.3v vddio local bu s dma read ? fast mode operating conditions ? vddc = 2.2 to 2.6v, vddio = 3.2 to 3.5v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split bus mode, read enable is the occurrence of dack# and optionally, ior#. for dma split bus mode, read enable is the occurrence of dack# and optionally, dmard#. 2. minimum value is guaranteed only if the dmareq register dma request enable bit is set. 3. eot#, dack#, and optionally, ior# or dmard#, must all be true for at least t24 for proper recognition of the eot# pulse. 4. a recovery time of 2 ns is required between dma read enable de-assertion and i/o read enable assertion. (this note is a general requirement not shown on the timing diagrams.) table 11-57. 3.3v vddio local bus dma read ? fast mode specifications symbol parameter min typ max unit notes t20 read enable true to dreq false 4 ? 19 ns 2 t21 read enable false to dreq true 4 35 45 ns t22 data access time from read enable ? ? 16 ns 1 t23 data three-state time from end of read enable 2 ? 12 ns 1 t24 eot# pulse width 10 ? ? ns 3 t25 dreq false to dreq true 15 35 ? ns t20 t21 t25 t20 t22 t23 t22 t23 t24 d0 d1 0ns 50ns 100ns 150ns 200ns dreq dack# ior# (optional) ld[15:0] eot# (optional)
electrical specifications plx technology, inc. 142 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 11.4.6.10 3.3v vddio local bus dma read ? burst mode operating conditions ? vddc = 2.2 to 2.6v, vddio = 3.2 to 3.5v, t a = 0 to 85c, output load = 25 pf notes: 1. for non-dma split bus mode, read enable is the occurrence of dack# and optionally, ior#. for dma split bus mode, read enable is the occurrence of dack# and optionally, dmard#. 3. eot#, dack#, and optionally, ior# or dmard#, must all be true for at least t24 for proper recognition of the eot# pulse. 4. a recovery time of 2 ns is required between dma read enable de-assertion and i/o read enable assertion. (this note is a general requirement not shown on the timing diagrams.) table 11-58. 3.3v vddio local bus dma read ? burst mode specifications symbol parameter min typ max unit notes t17 dma read cycle time 35 ? ? ns t18 dma read recovery time 19 ? ? ns t20 read enable true to dreq false 4 ? 20 ns t22 data access time from read enable ? ? 16 ns 1 t23 data three-state time from end of read enable 2 ? 12 ns 1 t24 eot# pulse width 10 ? ? ns 3 t20 t18 t17 t18 t17 t22 t23 t22 t23 t22 t23 t24 d0 d2 d1 0ns 25ns 50ns 75ns 100ns 125ns 150ns dreq dack# ior# (optional) ld[15:0] eot# (optional)
net2272 local bus to usb 2.0 peripheral controller data book 143 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 chapter 12 mechanical specifications 12.1 64-pin plastic tqfp (10 x 10 mm) figure 12-1. net2272 mechanical drawing (64-pin plastic tqfp package) m 16 1 17 33 49 64 j h c d b 32 48 p q s r l k g f i m n () detail of lead end note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters inches a 12.00.2 0.472 0.055 0.045 7 3 0.009 0.008 b 10.00.2 0.394 0.008 0.009 c 10.00.2 0.394 0.008 0.009 d 12.00.2 0.472 0.009 0.008 f 1.25 0.049 g 1.25 0.049 h 0.22 0.0090.002 i 0.10 0.004 j 0.5 (t.p.) 0.020 (t.p.) k 1.00.2 0.039 0.009 0.008 l 0.50.2 0.020 0.008 0.009 l p m 0.145 0.0060.002 0.055 0.045 n 0.10 0.004 p 1.00.1 0.039 0.005 0.004 q 0.10.05 0.0040.002 r 3 3 7 3 s 1.27 max 0.050 max a
mechanical specifications plx technology, inc. 144 net2272 local bus to usb 2.0 peripheral controller data book copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 12.2 64-ball plastic fbga (6 x 6 mm) figure 12-2. net2272 mechanical drawing (64-ball plastic fbga package)
net2272 local bus to usb 2.0 peripheral controller data book 145 copyright ? 2005 by plx technology, inc. all rights reserved - version 1.91 appendix a general information a.1 product ordering information contact your local plx sales representative for ordering information. where: net = netchip usb 2.0 controller product family 2272 = local bus to usb 2.0 peripheral controller rev1a = silicon revision b = package type (fbga) (if available) c = 0 to +70c commercial operating temperature range (if available) lf, f = lead-free rohs packaging (if available) a.2 united states and international representatives, and distributors plx technology, inc., representatives and distributors are listed at www.plxtech.com . a.3 technical support plx technology, inc., technical support information is listed at www.plxtech.com/support/ , or call 408 774-9060 or 800 759-3735. table a-1. product ordering information part numbers description NET2272REV1A-LF lead-free rohs green 64-pin plastic tqfp local bus to usb 2.0 hi-speed peripheral controller, 10 x 10 mm net2272rev1a-bc f lead-free rohs green 64-ball plastic fbga local bus to usb 2.0 hi-speed peripheral controller, 6 x 6 mm net2272pci-rdk net2272 re ference design kit

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